rvv: add control instructions and system register access

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/decode.h

@@ -138,6 +138,7 @@ private:
 // helpful macros, etc
 #define MMU (*p->get_mmu())
 #define STATE (*p->get_state())
+#define P (*p)
 #define READ_REG(reg) STATE.XPR[reg]
 #define READ_FREG(reg) STATE.FPR[reg]
 #define RS1 READ_REG(insn.rs1())

riscv/insns/vsetvl.h

@@ -0,0 +1 @@
+WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, RS2));

riscv/insns/vsetvli.h

@@ -0,0 +1 @@
+WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, insn.v_zimm11()));

riscv/processor.cc

@@ -647,6 +647,27 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_DSCRATCH:
       state.dscratch = val;
       break;
+    case CSR_VSTART:
+      VU.vstart = val;
+      break;
+    case CSR_VXSAT:
+      VU.vxsat = val;
+      break;
+    case CSR_VXRM:
+      VU.vxrm = val;
+      break;
+    case CSR_VL:
+      VU.vl = val;
+      break;
+    case CSR_VTYPE:
+      VU.vtype = val;
+      // check vill bit
+      if (BITS(VU.vtype, get_xlen(), get_xlen() - 1) == 1){
+        VU.vill = true;
+      }else{
+        VU.vill = false;
+      }
+      break;
   }
 }
 
@@ -814,6 +835,16 @@ reg_t processor_t::get_csr(int which)
       return state.dpc & pc_alignment_mask();
     case CSR_DSCRATCH:
       return state.dscratch;
+    case CSR_VSTART:
+      return VU.vstart;
+    case CSR_VXSAT:
+      return VU.vxsat;
+    case CSR_VXRM:
+      return VU.vxrm;
+    case CSR_VL:
+      return VU.vl;
+    case CSR_VTYPE:
+      return VU.vtype;
   }
   throw trap_illegal_instruction(0);
 }

riscv/riscv.mk.in

@@ -291,6 +291,13 @@ riscv_insn_ext_q = \
 	fsqrt_q \
 	fsub_q \
 
+riscv_insn_ext_v_ctrl = \
+	vsetvli \
+	vsetvl \
+
+riscv_insn_ext_v = \
+	$(riscv_insn_ext_v_ctrl) \
+
 riscv_insn_priv = \
 	csrrc \
 	csrrci \
@@ -315,6 +322,7 @@ riscv_insn_list = \
 	$(riscv_insn_ext_f) \
 	$(riscv_insn_ext_d) \
 	$(riscv_insn_ext_q) \
+	$(riscv_insn_ext_v) \
 	$(riscv_insn_priv) \
 
 riscv_gen_srcs = \