rvv: handle inactive and NaN case for vfredsum

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/decode.h

@@ -1691,11 +1691,13 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
 #define VI_VFP_LOOP_REDUCTION_BASE(width) \
   float##width##_t vd_0 = P.VU.elt<float##width##_t>(rd_num, 0); \
   float##width##_t vs1_0 = P.VU.elt<float##width##_t>(rs1_num, 0); \
-  vd_0 = vs1_0;\
+  vd_0 = vs1_0; \
+  bool is_active = false; \
   for (reg_t i=P.VU.vstart; i<vl; ++i){ \
     VI_LOOP_ELEMENT_SKIP(); \
     int##width##_t &vd = P.VU.elt<int##width##_t>(rd_num, i, true); \
     float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); \
+    is_active = true; \
 
 #define VI_VFP_LOOP_WIDE_REDUCTION_BASE \
   VI_VFP_COMMON \
@@ -1711,7 +1713,51 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   } \
   P.VU.vstart = 0; \
   if (vl > 0) { \
-    P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+    if (is_propagate && !is_active) { \
+      switch (x) { \
+        case e16: {\
+            auto ret = f16_classify(f16(vd_0.v)); \
+            if (ret & 0x300) { \
+              if (ret & 0x100) { \
+                softfloat_exceptionFlags |= softfloat_flag_invalid; \
+                set_fp_exceptions; \
+              } \
+              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = defaultNaNF16UI; \
+            } else { \
+              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+            } \
+          } \
+          break; \
+        case e32: { \
+            auto ret = f32_classify(f32(vd_0.v)); \
+            if (ret & 0x300) { \
+              if (ret & 0x100) { \
+                softfloat_exceptionFlags |= softfloat_flag_invalid; \
+                set_fp_exceptions; \
+              } \
+              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = defaultNaNF32UI; \
+            } else { \
+              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+            } \
+          } \
+          break; \
+        case e64: {\
+            auto ret = f64_classify(f64(vd_0.v)); \
+            if (ret & 0x300) { \
+              if (ret & 0x100) { \
+                softfloat_exceptionFlags |= softfloat_flag_invalid; \
+                set_fp_exceptions; \
+              } \
+              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = defaultNaNF64UI; \
+            } else { \
+              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+            } \
+          } \
+          break; \
+      } \
+    } else { \
+      P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+    } \
   }
 
 #define VI_VFP_LOOP_CMP_END \
@@ -1799,11 +1845,13 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   VI_VFP_COMMON \
   require((P.VU.vsew == e16 && p->supports_extension('F')) || \
           (P.VU.vsew == e32 && p->supports_extension('D'))); \
+  bool is_active = false; \
   switch(P.VU.vsew) { \
     case e16: {\
       float32_t vd_0 = P.VU.elt<float32_t>(rs1_num, 0); \
       for (reg_t i=P.VU.vstart; i<vl; ++i) { \
         VI_LOOP_ELEMENT_SKIP(); \
+        is_active = true; \
         float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \
         BODY16; \
         set_fp_exceptions; \
@@ -1814,6 +1862,7 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
       float64_t vd_0 = P.VU.elt<float64_t>(rs1_num, 0); \
       for (reg_t i=P.VU.vstart; i<vl; ++i) { \
         VI_LOOP_ELEMENT_SKIP(); \
+        is_active = true; \
         float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
         BODY32; \
         set_fp_exceptions; \

riscv/insns/vfredmax_vs.h

@@ -1,4 +1,5 @@
 // vfredmax vd, vs2, vs1
+bool is_propagate = false;
 VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f16_max(vd_0, vs2);

riscv/insns/vfredmin_vs.h

@@ -1,4 +1,5 @@
 // vfredmin vd, vs2, vs1
+bool is_propagate = false;
 VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f16_min(vd_0, vs2);

riscv/insns/vfredosum_vs.h

@@ -1,4 +1,5 @@
 // vfredosum: vd[0] =  sum( vs2[*] , vs1[0] )
+bool is_propagate = false;
 VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f16_add(vd_0, vs2);

riscv/insns/vfredsum_vs.h

@@ -1,4 +1,5 @@
 // vfredsum: vd[0] =  sum( vs2[*] , vs1[0] )
+bool is_propagate = true;
 VI_VFP_VV_LOOP_REDUCTION
 ({
   vd_0 = f16_add(vd_0, vs2);

riscv/insns/vfwredosum_vs.h

@@ -1,4 +1,5 @@
 // vfwredosum.vs vd, vs2, vs1
+bool is_propagate = false;
 VI_VFP_VV_LOOP_WIDE_REDUCTION
 ({
   vd_0 = f32_add(vd_0, vs2);

riscv/insns/vfwredsum_vs.h

@@ -1,4 +1,5 @@
 // vfwredsum.vs vd, vs2, vs1
+bool is_propagate = true;
 VI_VFP_VV_LOOP_WIDE_REDUCTION
 ({
   vd_0 = f32_add(vd_0, vs2);