fix htif interaction with interactive mode

riscv/interactive.cc

@@ -242,8 +242,6 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector<std::str
       current = get_pc(args2);
     else if(scmd == "mem")
       current = get_mem(args2);
-    else if(scmd == "tohost")
-      current = tohost;
     else
       return;
 

riscv/sim.cc

@@ -12,10 +12,9 @@
 
 sim_t::sim_t(int _nprocs, htif_t* _htif)
   : htif(_htif),
-    tohost(0),
-    fromhost(0),
     procs(_nprocs),
-    running(false)
+    running(false),
+    steps(0)
 {
   // allocate target machine's memory, shrinking it as necessary
   // until the allocation succeeds
@@ -69,7 +68,7 @@ void sim_t::run(bool debug)
   // word 1 of memory contains the core count
   mmu->store_uint32(4, num_cores());
 
-  //htif->wait_for_start();
+  htif->wait_for_start();
 
   for(running = true; running; )
   {
@@ -82,8 +81,12 @@ void sim_t::run(bool debug)
 
 void sim_t::step_all(size_t n, size_t interleave, bool noisy)
 {
-  htif->wait_for_packet();
   for(size_t j = 0; j < n; j+=interleave)
+  {
+    if (steps % 16384 + interleave >= 16384)
+      htif->wait_for_packet();
+    steps += interleave;
     for(int i = 0; i < (int)num_cores(); i++)
       procs[i]->step(interleave,noisy);
+  }
 }

riscv/sim.h

@@ -27,10 +27,6 @@ public:
 private:
   htif_t* htif;
 
-  // global registers for communication with host machine
-  reg_t tohost;
-  reg_t fromhost;
-
   // main memory, shared between processors
   char* mem;
   size_t memsz; // memory size in bytes
@@ -42,6 +38,7 @@ private:
   // terminate the simulation loop after the current iteration
   void stop() { running = false; }
   bool running;
+  size_t steps;
 
   // run each processor for n instructions; interleave instructions are
   // run on a processor before moving on to the next processor.