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riscv-isa-sim
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rvv: index load/store have benn separated into ordered and unordered parts (#611) 

ref:
  511d0b84a3

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/614/head
Chih-Min Chao 6 years ago
committed by GitHub
parent
654480447f
commit
21458a2710
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
19 changed files with 129 additions and 88 deletions
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  1. 12
      disasm/disasm.cc
  2. 168
      riscv/encoding.h
  3. 0
      riscv/insns/vloxei16_v.h
  4. 0
      riscv/insns/vloxei32_v.h
  5. 0
      riscv/insns/vloxei64_v.h
  6. 0
      riscv/insns/vloxei8_v.h
  7. 2
      riscv/insns/vluxei16_v.h
  8. 2
      riscv/insns/vluxei32_v.h
  9. 3
      riscv/insns/vluxei64_v.h
  10. 2
      riscv/insns/vluxei8_v.h
  11. 0
      riscv/insns/vsoxei16_v.h
  12. 0
      riscv/insns/vsoxei32_v.h
  13. 0
      riscv/insns/vsoxei64_v.h
  14. 0
      riscv/insns/vsoxei8_v.h
  15. 2
      riscv/insns/vsuxei16_v.h
  16. 2
      riscv/insns/vsuxei32_v.h
  17. 2
      riscv/insns/vsuxei64_v.h
  18. 2
      riscv/insns/vsuxei8_v.h
  19. 20
      riscv/riscv.mk.in

12
disasm/disasm.cc
View File

@ -767,12 +767,13 @@ disassembler_t::disassembler_t(int xlen)
std::vector<const arg_t *> v_st_index = {&vs3, &v_address, &vs2, &opt, &vm};
DISASM_VMEM_INSN(vle, v_ld_unit, );
DISASM_VMEM_INSN(vluxei, v_ld_index, );
DISASM_VMEM_INSN(vlse, v_ld_stride, );
DISASM_VMEM_INSN(vlxei, v_ld_index, );
DISASM_VMEM_INSN(vloxei, v_ld_index, );
DISASM_VMEM_INSN(vle, v_ld_unit, ff);
DISASM_VMEM_INSN(vse, v_st_unit, );
DISASM_VMEM_INSN(vsoxei, v_st_index, );
DISASM_VMEM_INSN(vsse, v_st_stride, );
DISASM_VMEM_INSN(vsxei, v_st_index, );
DISASM_VMEM_INSN(vsuxei, v_st_index, );
#undef DISASM_VMEM_INSN
@ -783,11 +784,14 @@ disassembler_t::disassembler_t(int xlen)
{match_vle8_v, mask_vle8_v, "vlseg%de%d.v", v_ld_unit},
{match_vse8_v, mask_vse8_v, "vsseg%de%d.v", v_st_unit},
{match_vluxei8_v, mask_vluxei8_v, "vluxseg%dei%d.v", v_ld_index},
{match_vsuxei8_v, mask_vsuxei8_v, "vsuxseg%dei%d.v", v_st_index},
{match_vlse8_v, mask_vlse8_v, "vlsseg%de%d.v", v_ld_stride},
{match_vsse8_v, mask_vsse8_v, "vssseg%de%d.v", v_st_stride},
{match_vlxei8_v, mask_vlxei8_v, "vlxseg%dei%d.v", v_ld_index},
{match_vsxei8_v, mask_vsxei8_v, "vsxseg%dei%d.v", v_st_index},
{match_vloxei8_v, mask_vloxei8_v, "vloxseg%dei%d.v", v_ld_index},
{match_vsoxei8_v, mask_vsoxei8_v, "vsoxseg%dei%d.v", v_st_index},
{match_vle8ff_v, mask_vle8ff_v, "vlseg%de%dff.v", v_ld_unit}
};

168
riscv/encoding.h
View File

@ -1215,6 +1215,38 @@
#define MASK_VSE512_V 0x1df0707f
#define MATCH_VSE1024_V 0x10007027
#define MASK_VSE1024_V 0x1df0707f
#define MATCH_VLUXEI8_V 0x4000007
#define MASK_VLUXEI8_V 0x1c00707f
#define MATCH_VLUXEI16_V 0x4005007
#define MASK_VLUXEI16_V 0x1c00707f
#define MATCH_VLUXEI32_V 0x4006007
#define MASK_VLUXEI32_V 0x1c00707f
#define MATCH_VLUXEI64_V 0x4007007
#define MASK_VLUXEI64_V 0x1c00707f
#define MATCH_VLUXEI128_V 0x14000007
#define MASK_VLUXEI128_V 0x1c00707f
#define MATCH_VLUXEI256_V 0x14005007
#define MASK_VLUXEI256_V 0x1c00707f
#define MATCH_VLUXEI512_V 0x14006007
#define MASK_VLUXEI512_V 0x1c00707f
#define MATCH_VLUXEI1024_V 0x14007007
#define MASK_VLUXEI1024_V 0x1c00707f
#define MATCH_VSUXEI8_V 0x4000027
#define MASK_VSUXEI8_V 0x1c00707f
#define MATCH_VSUXEI16_V 0x4005027
#define MASK_VSUXEI16_V 0x1c00707f
#define MATCH_VSUXEI32_V 0x4006027
#define MASK_VSUXEI32_V 0x1c00707f
#define MATCH_VSUXEI64_V 0x4007027
#define MASK_VSUXEI64_V 0x1c00707f
#define MATCH_VSUXEI128_V 0x14000027
#define MASK_VSUXEI128_V 0x1c00707f
#define MATCH_VSUXEI256_V 0x14005027
#define MASK_VSUXEI256_V 0x1c00707f
#define MATCH_VSUXEI512_V 0x14006027
#define MASK_VSUXEI512_V 0x1c00707f
#define MATCH_VSUXEI1024_V 0x14007027
#define MASK_VSUXEI1024_V 0x1c00707f
#define MATCH_VLSE8_V 0x8000007
#define MASK_VLSE8_V 0x1c00707f
#define MATCH_VLSE16_V 0x8005007
@ -1247,54 +1279,38 @@
#define MASK_VSSE512_V 0x1c00707f
#define MATCH_VSSE1024_V 0x18007027
#define MASK_VSSE1024_V 0x1c00707f
#define MATCH_VLXEI8_V 0xc000007
#define MASK_VLXEI8_V 0x1c00707f
#define MATCH_VLXEI16_V 0xc005007
#define MASK_VLXEI16_V 0x1c00707f
#define MATCH_VLXEI32_V 0xc006007
#define MASK_VLXEI32_V 0x1c00707f
#define MATCH_VLXEI64_V 0xc007007
#define MASK_VLXEI64_V 0x1c00707f
#define MATCH_VLXEI128_V 0x1c000007
#define MASK_VLXEI128_V 0x1c00707f
#define MATCH_VLXEI256_V 0x1c005007
#define MASK_VLXEI256_V 0x1c00707f
#define MATCH_VLXEI512_V 0x1c006007
#define MASK_VLXEI512_V 0x1c00707f
#define MATCH_VLXEI1024_V 0x1c007007
#define MASK_VLXEI1024_V 0x1c00707f
#define MATCH_VSXEI8_V 0xc000027
#define MASK_VSXEI8_V 0x1c00707f
#define MATCH_VSXEI16_V 0xc005027
#define MASK_VSXEI16_V 0x1c00707f
#define MATCH_VSXEI32_V 0xc006027
#define MASK_VSXEI32_V 0x1c00707f
#define MATCH_VSXEI64_V 0xc007027
#define MASK_VSXEI64_V 0x1c00707f
#define MATCH_VSXEI128_V 0x1c000027
#define MASK_VSXEI128_V 0x1c00707f
#define MATCH_VSXEI256_V 0x1c005027
#define MASK_VSXEI256_V 0x1c00707f
#define MATCH_VSXEI512_V 0x1c006027
#define MASK_VSXEI512_V 0x1c00707f
#define MATCH_VSXEI1024_V 0x1c007027
#define MASK_VSXEI1024_V 0x1c00707f
#define MATCH_VSUXEI8_V 0x4000027
#define MASK_VSUXEI8_V 0x1c00707f
#define MATCH_VSUXEI16_V 0x4005027
#define MASK_VSUXEI16_V 0x1c00707f
#define MATCH_VSUXEI32_V 0x4006027
#define MASK_VSUXEI32_V 0x1c00707f
#define MATCH_VSUXEI64_V 0x4007027
#define MASK_VSUXEI64_V 0x1c00707f
#define MATCH_VSUXEI128_V 0x14000027
#define MASK_VSUXEI128_V 0x1c00707f
#define MATCH_VSUXEI256_V 0x14005027
#define MASK_VSUXEI256_V 0x1c00707f
#define MATCH_VSUXEI512_V 0x14006027
#define MASK_VSUXEI512_V 0x1c00707f
#define MATCH_VSUXEI1024_V 0x14007027
#define MASK_VSUXEI1024_V 0x1c00707f
#define MATCH_VLOXEI8_V 0xc000007
#define MASK_VLOXEI8_V 0x1c00707f
#define MATCH_VLOXEI16_V 0xc005007
#define MASK_VLOXEI16_V 0x1c00707f
#define MATCH_VLOXEI32_V 0xc006007
#define MASK_VLOXEI32_V 0x1c00707f
#define MATCH_VLOXEI64_V 0xc007007
#define MASK_VLOXEI64_V 0x1c00707f
#define MATCH_VLOXEI128_V 0x1c000007
#define MASK_VLOXEI128_V 0x1c00707f
#define MATCH_VLOXEI256_V 0x1c005007
#define MASK_VLOXEI256_V 0x1c00707f
#define MATCH_VLOXEI512_V 0x1c006007
#define MASK_VLOXEI512_V 0x1c00707f
#define MATCH_VLOXEI1024_V 0x1c007007
#define MASK_VLOXEI1024_V 0x1c00707f
#define MATCH_VSOXEI8_V 0xc000027
#define MASK_VSOXEI8_V 0x1c00707f
#define MATCH_VSOXEI16_V 0xc005027
#define MASK_VSOXEI16_V 0x1c00707f
#define MATCH_VSOXEI32_V 0xc006027
#define MASK_VSOXEI32_V 0x1c00707f
#define MATCH_VSOXEI64_V 0xc007027
#define MASK_VSOXEI64_V 0x1c00707f
#define MATCH_VSOXEI128_V 0x1c000027
#define MASK_VSOXEI128_V 0x1c00707f
#define MATCH_VSOXEI256_V 0x1c005027
#define MASK_VSOXEI256_V 0x1c00707f
#define MATCH_VSOXEI512_V 0x1c006027
#define MASK_VSOXEI512_V 0x1c00707f
#define MATCH_VSOXEI1024_V 0x1c007027
#define MASK_VSOXEI1024_V 0x1c00707f
#define MATCH_VLE8FF_V 0x1000007
#define MASK_VLE8FF_V 0x1df0707f
#define MATCH_VLE16FF_V 0x1005007
@ -2822,6 +2838,22 @@ DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V)
DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V)
DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V)
DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V)
DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V)
DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V)
DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V)
DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V)
DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V)
DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V)
DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V)
DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V)
DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V)
DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V)
DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V)
DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V)
DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V)
DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V)
DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V)
DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V)
DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V)
DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V)
DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V)
@ -2838,30 +2870,22 @@ DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V)
DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V)
DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V)
DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V)
DECLARE_INSN(vlxei8_v, MATCH_VLXEI8_V, MASK_VLXEI8_V)
DECLARE_INSN(vlxei16_v, MATCH_VLXEI16_V, MASK_VLXEI16_V)
DECLARE_INSN(vlxei32_v, MATCH_VLXEI32_V, MASK_VLXEI32_V)
DECLARE_INSN(vlxei64_v, MATCH_VLXEI64_V, MASK_VLXEI64_V)
DECLARE_INSN(vlxei128_v, MATCH_VLXEI128_V, MASK_VLXEI128_V)
DECLARE_INSN(vlxei256_v, MATCH_VLXEI256_V, MASK_VLXEI256_V)
DECLARE_INSN(vlxei512_v, MATCH_VLXEI512_V, MASK_VLXEI512_V)
DECLARE_INSN(vlxei1024_v, MATCH_VLXEI1024_V, MASK_VLXEI1024_V)
DECLARE_INSN(vsxei8_v, MATCH_VSXEI8_V, MASK_VSXEI8_V)
DECLARE_INSN(vsxei16_v, MATCH_VSXEI16_V, MASK_VSXEI16_V)
DECLARE_INSN(vsxei32_v, MATCH_VSXEI32_V, MASK_VSXEI32_V)
DECLARE_INSN(vsxei64_v, MATCH_VSXEI64_V, MASK_VSXEI64_V)
DECLARE_INSN(vsxei128_v, MATCH_VSXEI128_V, MASK_VSXEI128_V)
DECLARE_INSN(vsxei256_v, MATCH_VSXEI256_V, MASK_VSXEI256_V)
DECLARE_INSN(vsxei512_v, MATCH_VSXEI512_V, MASK_VSXEI512_V)
DECLARE_INSN(vsxei1024_v, MATCH_VSXEI1024_V, MASK_VSXEI1024_V)
DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V)
DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V)
DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V)
DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V)
DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V)
DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V)
DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V)
DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V)
DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V)
DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V)
DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V)
DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V)
DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V)
DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V)
DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V)
DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V)
DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V)
DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V)
DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V)
DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V)
DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V)
DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V)
DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V)
DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V)
DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V)
DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V)
DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V)

0
riscv/insns/vlxei16_v.h → riscv/insns/vloxei16_v.h
View File

0
riscv/insns/vlxei32_v.h → riscv/insns/vloxei32_v.h
View File

0
riscv/insns/vlxei64_v.h → riscv/insns/vloxei64_v.h
View File

0
riscv/insns/vlxei8_v.h → riscv/insns/vloxei8_v.h
View File

2
riscv/insns/vluxei16_v.h
View File

@ -0,0 +1,2 @@
// vlxei16.v and vlxseg[2-8]e16.v
VI_LD_INDEX(e16, true);

2
riscv/insns/vluxei32_v.h
View File

@ -0,0 +1,2 @@
// vlxe32.v and vlxseg[2-8]ei32.v
VI_LD_INDEX(e32, true);

3
riscv/insns/vluxei64_v.h
View File

@ -0,0 +1,3 @@
// vlxei64.v and vlxseg[2-8]ei64.v
VI_LD_INDEX(e64, true);

2
riscv/insns/vluxei8_v.h
View File

@ -0,0 +1,2 @@
// vlxei8.v and vlxseg[2-8]ei8.v
VI_LD_INDEX(e8, true);

0
riscv/insns/vsxei16_v.h → riscv/insns/vsoxei16_v.h
View File

0
riscv/insns/vsxei32_v.h → riscv/insns/vsoxei32_v.h
View File

0
riscv/insns/vsxei64_v.h → riscv/insns/vsoxei64_v.h
View File

0
riscv/insns/vsxei8_v.h → riscv/insns/vsoxei8_v.h
View File

2
riscv/insns/vsuxei16_v.h
View File

@ -1,2 +1,2 @@
// vsuxe16.v
VI_ST_INDEX(e16, false);
VI_ST_INDEX(e16, true);

2
riscv/insns/vsuxei32_v.h
View File

@ -1,2 +1,2 @@
// vsuxe32.v
VI_ST_INDEX(e32, false);
VI_ST_INDEX(e32, true);

2
riscv/insns/vsuxei64_v.h
View File

@ -1,2 +1,2 @@
// vsuxe64.v
VI_ST_INDEX(e64, false);
VI_ST_INDEX(e64, true);

2
riscv/insns/vsuxei8_v.h
View File

@ -1,2 +1,2 @@
// vsuxe8.v
VI_ST_INDEX(e8, false);
VI_ST_INDEX(e8, true);

20
riscv/riscv.mk.in
View File

@ -799,14 +799,18 @@ riscv_insn_ext_v_ldst = \
vle16_v \
vle32_v \
vle64_v \
vloxei8_v \
vloxei16_v \
vloxei32_v \
vloxei64_v \
vlse8_v \
vlse16_v \
vlse32_v \
vlse64_v \
vlxei8_v \
vlxei16_v \
vlxei32_v \
vlxei64_v \
vluxei8_v \
vluxei16_v \
vluxei32_v \
vluxei64_v \
vle8ff_v \
vle16ff_v \
vle32ff_v \
@ -832,13 +836,13 @@ riscv_insn_ext_v_ldst = \
vse32_v \
vse64_v \
vsse8_v \
vsoxei8_v \
vsoxei16_v \
vsoxei32_v \
vsoxei64_v \
vsse16_v \
vsse32_v \
vsse64_v \
vsxei8_v \
vsxei16_v \
vsxei32_v \
vsxei64_v \
vsuxei8_v \
vsuxei16_v \
vsuxei32_v \

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