[sim] fixed FSR exception field bug · 2032e6c6b7 - riscv-isa-sim - Gitea: Git with a cup of tea

[sim] fixed FSR exception field bug

cs250

Andrew Waterman 15 years ago

parent

66eda0b75e

commit

2032e6c6b7

1 changed files with 1 additions and 1 deletions

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riscv/decode.h

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					@ -63,7 +63,7 @@ const int JUMP_ALIGN_BITS = 1;
				
					#define FPEXC_NX 0x01
					
					#define FPEXC_NX 0x01
				
					#define FPEXC_UF 0x02
					
					#define FPEXC_UF 0x02
				
					#define FPEXC_OF 0x04
					
					#define FPEXC_OF 0x04
				
					#define FPEXC_DZ 0x02
					
					#define FPEXC_DZ 0x08
				
					#define FPEXC_NV 0x10
					
					#define FPEXC_NV 0x10
				
					#define FSR_AEXC_SHIFT 0
					
					#define FSR_AEXC_SHIFT 0