Merge [shm]call into ecall, [shm]ret into eret

11 years ago · 1fbcb3dfe3
7 changed files with 24 additions and 38 deletions
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@ -150,14 +150,10 @@
 #define MASK_AMOMAX_D  0xf800707f
 #define MATCH_BLTU 0x6063
 #define MASK_BLTU  0x707f
-#define MATCH_FCLASS_S 0xe0001053
-#define MASK_FCLASS_S  0xfff0707f
 #define MATCH_FSGNJN_D 0x22001053
 #define MASK_FSGNJN_D  0xfe00707f
-#define MATCH_HCALL 0x10000073
-#define MASK_HCALL  0xffffffff
-#define MATCH_MRET 0x30200073
-#define MASK_MRET  0xffffffff
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
 #define MATCH_CSRRW 0x1073
 #define MASK_CSRRW  0x707f
 #define MATCH_SLLIW 0x101b
@ -244,9 +240,9 @@
 #define MASK_BLT  0x707f
 #define MATCH_SCALL 0x73
 #define MASK_SCALL  0xffffffff
-#define MATCH_FMIN_S 0x28000053
-#define MASK_FMIN_S  0xfe00707f
-#define MATCH_SFENCE_VM 0x10400073
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_SFENCE_VM 0x10100073
 #define MASK_SFENCE_VM  0xfff07fff
 #define MATCH_SC_W 0x1800202f
 #define MASK_SC_W  0xf800707f
@ -264,8 +260,6 @@
 #define MASK_MULH  0xfe00707f
 #define MATCH_FMUL_S 0x10000053
 #define MASK_FMUL_S  0xfe00007f
-#define MATCH_MCALL 0x20000073
-#define MASK_MCALL  0xffffffff
 #define MATCH_CSRRSI 0x6073
 #define MASK_CSRRSI  0x707f
 #define MATCH_SRAI 0x40005013
@ -306,7 +300,7 @@
 #define MASK_FSUB_D  0xfe00007f
 #define MATCH_FSGNJX_S 0x20002053
 #define MASK_FSGNJX_S  0xfe00707f
-#define MATCH_MRTS 0x30900073
+#define MATCH_MRTS 0x30500073
 #define MASK_MRTS  0xffffffff
 #define MATCH_FEQ_D 0xa2002053
 #define MASK_FEQ_D  0xfe00707f
@ -334,7 +328,7 @@
 #define MASK_ANDI  0x707f
 #define MATCH_FMV_X_S 0xe0000053
 #define MASK_FMV_X_S  0xfff0707f
-#define MATCH_SRET 0x10200073
+#define MATCH_SRET 0x10000073
 #define MASK_SRET  0xffffffff
 #define MATCH_FNMADD_S 0x4f
 #define MASK_FNMADD_S  0x600007f
@ -516,14 +510,12 @@
 #define CAUSE_MISALIGNED_FETCH 0x0
 #define CAUSE_FAULT_FETCH 0x1
 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
-#define CAUSE_SCALL 0x4
-#define CAUSE_HCALL 0x5
-#define CAUSE_MCALL 0x6
-#define CAUSE_BREAKPOINT 0x7
-#define CAUSE_MISALIGNED_LOAD 0x8
-#define CAUSE_FAULT_LOAD 0x9
-#define CAUSE_MISALIGNED_STORE 0xa
-#define CAUSE_FAULT_STORE 0xb
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_ECALL 0x8
+#define CAUSE_BREAKPOINT 0x9
 #endif
 #ifdef DECLARE_INSN
 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
@ -532,10 +524,8 @@ DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-DECLARE_INSN(hcall, MATCH_HCALL, MASK_HCALL)
-DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
@ -579,7 +569,7 @@ DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
@ -589,7 +579,6 @@ DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-DECLARE_INSN(mcall, MATCH_MCALL, MASK_MCALL)
 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
--- a/riscv/insns/hcall.h
+++ b/riscv/insns/hcall.h
@ -1,2 +0,0 @@
-require_privilege(PRV_S);
-throw trap_hcall();
--- a/riscv/insns/mcall.h
+++ b/riscv/insns/mcall.h
@ -1 +0,0 @@
-throw trap_illegal_instruction();
--- a/riscv/insns/mret.h
+++ b/riscv/insns/mret.h
@ -1,3 +0,0 @@
-require_privilege(PRV_M);
-p->pop_privilege_stack();
-set_pc(p->get_state()->mepc);
--- a/riscv/insns/scall.h
+++ b/riscv/insns/scall.h
@ -1 +1 @@
-throw trap_scall();
+throw trap_ecall();
--- a/riscv/insns/sret.h
+++ b/riscv/insns/sret.h
@ -1,3 +1,8 @@
 require_privilege(PRV_S);
+switch (get_field(STATE.mstatus, MSTATUS_PRV))
+{
+  case PRV_S: set_pc(p->get_state()->sepc); break;
+  case PRV_M: set_pc(p->get_state()->mepc); break;
+  default: abort();
+}
 p->pop_privilege_stack();
-set_pc(p->get_state()->sepc);
--- a/riscv/trap.h
+++ b/riscv/trap.h
@ -45,13 +45,11 @@ class mem_trap_t : public trap_t
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
 DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_TRAP(CAUSE_SCALL, scall)
-DECLARE_TRAP(CAUSE_HCALL, hcall)
-DECLARE_TRAP(CAUSE_MCALL, mcall)
-DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault)
 DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault)
+DECLARE_TRAP(CAUSE_ECALL, ecall)
+DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)

 #endif