Simplify vmerge, vfmerge

riscv/decode.h

@@ -960,23 +960,84 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
   VI_LOOP_CMP_END
 
 // merge and copy loop
-#define VI_VVXI_MERGE_LOOP(BODY) \
+#define VI_MERGE_VARS \
+  VI_MASK_VARS \
+  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
+
+#define VI_MERGE_LOOP_BASE \
+  require_vector(true); \
   VI_GENERAL_LOOP_BASE \
+  VI_MERGE_VARS
+
+#define VI_VV_MERGE_LOOP(BODY) \
+  VI_CHECK_SSS(true); \
+  VI_MERGE_LOOP_BASE \
   if (sew == e8){ \
-    VXI_PARAMS(e8); \
+    VV_PARAMS(e8); \
     BODY; \
   }else if(sew == e16){ \
-    VXI_PARAMS(e16); \
+    VV_PARAMS(e16); \
     BODY; \
   }else if(sew == e32){ \
-    VXI_PARAMS(e32); \
+    VV_PARAMS(e32); \
     BODY; \
   }else if(sew == e64){ \
-    VXI_PARAMS(e64); \
+    VV_PARAMS(e64); \
+    BODY; \
+  } \
+  VI_LOOP_END
+
+#define VI_VX_MERGE_LOOP(BODY) \
+  VI_CHECK_SSS(false); \
+  VI_MERGE_LOOP_BASE \
+  if (sew == e8){ \
+    VX_PARAMS(e8); \
+    BODY; \
+  }else if(sew == e16){ \
+    VX_PARAMS(e16); \
+    BODY; \
+  }else if(sew == e32){ \
+    VX_PARAMS(e32); \
+    BODY; \
+  }else if(sew == e64){ \
+    VX_PARAMS(e64); \
     BODY; \
   } \
   VI_LOOP_END 
 
+#define VI_VI_MERGE_LOOP(BODY) \
+  VI_CHECK_SSS(false); \
+  VI_MERGE_LOOP_BASE \
+  if (sew == e8){ \
+    VI_PARAMS(e8); \
+    BODY; \
+  }else if(sew == e16){ \
+    VI_PARAMS(e16); \
+    BODY; \
+  }else if(sew == e32){ \
+    VI_PARAMS(e32); \
+    BODY; \
+  }else if(sew == e64){ \
+    VI_PARAMS(e64); \
+    BODY; \
+  } \
+  VI_LOOP_END
+
+#define VI_VF_MERGE_LOOP(BODY) \
+  VI_CHECK_SSS(false); \
+  VI_MERGE_LOOP_BASE \
+  if(sew == e16){ \
+    VFP_VF_PARAMS(16); \
+    BODY; \
+  }else if(sew == e32){ \
+    VFP_VF_PARAMS(32); \
+    BODY; \
+  }else if(sew == e64){ \
+    VFP_VF_PARAMS(64); \
+    BODY; \
+  } \
+  VI_LOOP_END
+
 // reduction loop - signed
 #define VI_LOOP_REDUCTION_BASE(x) \
   require(x >= e8 && x <= e64); \

riscv/insns/vfmerge_vfm.h

@@ -1,44 +1,4 @@
 // vfmerge_vf vd, vs2, vs1, vm
-VI_CHECK_SSS(false);
-VI_VFP_COMMON;
-
-switch(P.VU.vsew) {
-  case e16:
-    for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
-      VFP_VF_PARAMS(16);
-
-      int midx = i / 64;
-      int mpos = i % 64;
-      bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-
-      vd = use_first ? rs1 : vs2;
-    }
-    break;
-  case e32:
-    for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
-      VFP_VF_PARAMS(32);
-
-      int midx = i / 64;
-      int mpos = i % 64;
-      bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-
-      vd = use_first ? rs1 : vs2;
-    }
-    break;
-  case e64:
-    for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
-      VFP_VF_PARAMS(64);
-
-      int midx = i / 64;
-      int mpos = i % 64;
-      bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-
-      vd = use_first ? rs1 : vs2;
-    }
-    break;
-  default:
-    require(0);
-    break;
-}
-
-P.VU.vstart->write(0);
+VI_VF_MERGE_LOOP({
+  vd = use_first ? rs1 : vs2;
+})

riscv/insns/vmerge_vim.h

@@ -1,11 +1,5 @@
 // vmerge.vim vd, vs2, simm5
-require_vector(true);
-VI_CHECK_SSS(false);
-VI_VVXI_MERGE_LOOP
+VI_VI_MERGE_LOOP
 ({
-  int midx = i / 64;
-  int mpos = i % 64;
-  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-
   vd = use_first ? simm5 : vs2;
 })

riscv/insns/vmerge_vvm.h

@@ -1,11 +1,5 @@
 // vmerge.vvm vd, vs2, vs1
-require_vector(true);
-VI_CHECK_SSS(true);
-VI_VVXI_MERGE_LOOP
+VI_VV_MERGE_LOOP
 ({
-  int midx = i / 64;
-  int mpos = i % 64;
-  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-
   vd = use_first ? vs1 : vs2;
 })

riscv/insns/vmerge_vxm.h

@@ -1,11 +1,5 @@
 // vmerge.vxm vd, vs2, rs1
-require_vector(true);
-VI_CHECK_SSS(false);
-VI_VVXI_MERGE_LOOP
+VI_VX_MERGE_LOOP
 ({
-  int midx = i / 64;
-  int mpos = i % 64;
-  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-
   vd = use_first ? rs1 : vs2;
 })

riscv/insns/vmv_v_i.h

@@ -1,7 +1,5 @@
 // vmv.v.i vd, simm5
-require_vector(true);
-VI_CHECK_SSS(false);
-VI_VVXI_MERGE_LOOP
+VI_VI_MERGE_LOOP
 ({
   vd = simm5;
 })

riscv/insns/vmv_v_v.h

@@ -1,7 +1,5 @@
 // vvmv.v.v vd, vs1
-require_vector(true);
-VI_CHECK_SSS(true);
-VI_VVXI_MERGE_LOOP
+VI_VV_MERGE_LOOP
 ({
   vd = vs1;
 })

riscv/insns/vmv_v_x.h

@@ -1,7 +1,5 @@
 // vmv.v.x vd, rs1
-require_vector(true);
-VI_CHECK_SSS(false);
-VI_VVXI_MERGE_LOOP
+VI_VX_MERGE_LOOP
 ({
   vd = rs1;
 })