From 1ef7fe3e19dcce408cec3e0236a24de6088fb976 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Mon, 8 Mar 2021 18:35:06 -0800 Subject: [PATCH] When disabling hypervisor via misa, clear hypervisor state Otherwise, mstatus.MPV and hstatus.SPV could remain 1, and executing mret/sret would then set state.v=1, which would be bad since hypervisor's supposed to be disabled. --- riscv/processor.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index b551a333..07206050 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1130,11 +1130,17 @@ void processor_t::set_csr(int which, reg_t val) state.misa = (val & mask) | (state.misa & ~mask); - // update the forced bits in MIDELEG + // update the forced bits in MIDELEG and other CSRs if (supports_extension('H')) state.mideleg |= MIDELEG_FORCED_MASK; - else + else { state.mideleg &= ~MIDELEG_FORCED_MASK; + state.medeleg &= ~hypervisor_exceptions; + state.mstatus &= ~(MSTATUS_GVA | MSTATUS_MPV); + state.mie &= ~MIP_HS_MASK; // also takes care of hip, sip, hvip + state.mip &= ~MIP_HS_MASK; // also takes care of hie, sie + set_csr(CSR_HSTATUS, 0); + } break; } case CSR_HSTATUS: {