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Delete --enable-misaligned configure option

pull/1206/head
Andrew Waterman 3 years ago
parent
commit
1aac9da38f
  1. 3
      config.h.in
  2. 16
      configure
  3. 5
      riscv/riscv.ac

3
config.h.in

@ -105,9 +105,6 @@
/* Enable support for running target in either endianness */
#undef RISCV_ENABLE_DUAL_ENDIAN
/* Enable hardware support for misaligned loads and stores */
#undef RISCV_ENABLE_MISALIGNED
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef SOFTFLOAT_ENABLED

16
configure

@ -716,7 +716,6 @@ with_priv
with_varch
with_target
enable_dirty
enable_misaligned
enable_dual_endian
'
ac_precious_vars='build_alias
@ -1362,8 +1361,6 @@ Optional Features:
Enable all optional subprojects
--enable-dirty Enable hardware management of PTE accessed and dirty
bits
--enable-misaligned Enable hardware support for misaligned loads and
stores
--enable-dual-endian Enable support for running target in either
endianness
@ -6061,19 +6058,6 @@ if test "x$enable_dirty" = "xyes"; then :
$as_echo "#define RISCV_ENABLE_DIRTY /**/" >>confdefs.h
fi
# Check whether --enable-misaligned was given.
if test "${enable_misaligned+set}" = set; then :
enableval=$enable_misaligned;
fi
if test "x$enable_misaligned" = "xyes"; then :
$as_echo "#define RISCV_ENABLE_MISALIGNED /**/" >>confdefs.h
fi
# Check whether --enable-dual-endian was given.

5
riscv/riscv.ac

@ -44,11 +44,6 @@ AS_IF([test "x$enable_dirty" = "xyes"], [
AC_DEFINE([RISCV_ENABLE_DIRTY],,[Enable hardware management of PTE accessed and dirty bits])
])
AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardware support for misaligned loads and stores]))
AS_IF([test "x$enable_misaligned" = "xyes"], [
AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores])
])
AC_ARG_ENABLE([dual-endian], AS_HELP_STRING([--enable-dual-endian], [Enable support for running target in either endianness]))
AS_IF([test "x$enable_dual_endian" = "xyes"], [
AC_DEFINE([RISCV_ENABLE_DUAL_ENDIAN],,[Enable support for running target in either endianness])

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