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The ns16550 is a widely use serial device so we add a simplified ns16550 device emulation which is good enough for Linux, OpenSBI, and hypervisors to use as console. Signed-off-by: Anup Patel <anup@brainfault.org>pull/889/head
Anup Patel
5 years ago
8 changed files with 426 additions and 4 deletions
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#include <sys/time.h> |
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#include "devices.h" |
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#include "processor.h" |
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#include "term.h" |
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#define UART_QUEUE_SIZE 64 |
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#define UART_RX 0 /* In: Receive buffer */ |
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#define UART_TX 0 /* Out: Transmit buffer */ |
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#define UART_IER 1 /* Out: Interrupt Enable Register */ |
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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#define UART_IIR 2 /* In: Interrupt ID Register */ |
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ |
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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#define UART_IIR_TYPE_BITS 0xc0 |
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#define UART_FCR 2 /* Out: FIFO Control Register */ |
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ |
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
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#define UART_LCR 3 /* Out: Line Control Register */ |
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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#define UART_LCR_SBC 0x40 /* Set break control */ |
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ |
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#define UART_LCR_EPAR 0x10 /* Even parity select */ |
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#define UART_LCR_PARITY 0x08 /* Parity Enable */ |
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ |
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#define UART_MCR 4 /* Out: Modem Control Register */ |
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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#define UART_MCR_RTS 0x02 /* RTS complement */ |
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#define UART_MCR_DTR 0x01 /* DTR complement */ |
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#define UART_LSR 5 /* In: Line Status Register */ |
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#define UART_LSR_FIFOE 0x80 /* Fifo error */ |
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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#define UART_LSR_FE 0x08 /* Frame error indicator */ |
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#define UART_LSR_PE 0x04 /* Parity error indicator */ |
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#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ |
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#define UART_MSR 6 /* In: Modem Status Register */ |
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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#define UART_MSR_RI 0x40 /* Ring Indicator */ |
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#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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#define UART_MSR_CTS 0x10 /* Clear to Send */ |
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#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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#define UART_SCR 7 /* I/O: Scratch Register */ |
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ns16550_t::ns16550_t(class bus_t *bus, abstract_interrupt_controller_t *intctrl, |
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uint32_t interrupt_id, uint32_t reg_shift, uint32_t reg_io_width) |
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: bus(bus), intctrl(intctrl), interrupt_id(interrupt_id), reg_shift(reg_shift), reg_io_width(reg_io_width) |
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{ |
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ier = 0; |
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iir = UART_IIR_NO_INT; |
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fcr = 0; |
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lcr = 0; |
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lsr = UART_LSR_TEMT | UART_LSR_THRE; |
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msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
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dll = 0x0C; |
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mcr = UART_MCR_OUT2; |
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scr = 0; |
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} |
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void ns16550_t::update_interrupt(void) |
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{ |
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uint8_t interrupts = 0; |
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/* Handle clear rx */ |
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if (lcr & UART_FCR_CLEAR_RCVR) { |
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lcr &= ~UART_FCR_CLEAR_RCVR; |
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while (!rx_queue.empty()) { |
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rx_queue.pop(); |
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} |
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lsr &= ~UART_LSR_DR; |
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} |
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/* Handle clear tx */ |
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if (lcr & UART_FCR_CLEAR_XMIT) { |
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lcr &= ~UART_FCR_CLEAR_XMIT; |
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lsr |= UART_LSR_TEMT | UART_LSR_THRE; |
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} |
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/* Data ready and rcv interrupt enabled ? */ |
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if ((ier & UART_IER_RDI) && (lsr & UART_LSR_DR)) { |
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interrupts |= UART_IIR_RDI; |
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} |
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/* Transmitter empty and interrupt enabled ? */ |
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if ((ier & UART_IER_THRI) && (lsr & UART_LSR_TEMT)) { |
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interrupts |= UART_IIR_THRI; |
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} |
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/* Now update the interrup line, if necessary */ |
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if (!interrupts) { |
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iir = UART_IIR_NO_INT; |
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intctrl->set_interrupt_level(interrupt_id, 0); |
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} else { |
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iir = interrupts; |
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intctrl->set_interrupt_level(interrupt_id, 1); |
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} |
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/*
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* If the OS disabled the tx interrupt, we know that there is nothing |
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* more to transmit. |
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*/ |
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if (!(ier & UART_IER_THRI)) { |
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lsr |= UART_LSR_TEMT | UART_LSR_THRE; |
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} |
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} |
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uint8_t ns16550_t::rx_byte(void) |
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{ |
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uint8_t ret = 0; |
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if (rx_queue.empty()) { |
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lsr &= ~UART_LSR_DR; |
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return 0; |
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} |
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/* Break issued ? */ |
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if (lsr & UART_LSR_BI) { |
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lsr &= ~UART_LSR_BI; |
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return 0; |
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} |
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ret = rx_queue.front(); |
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rx_queue.pop(); |
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if (rx_queue.empty()) { |
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lsr &= ~UART_LSR_DR; |
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} |
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return ret; |
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} |
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void ns16550_t::tx_byte(uint8_t val) |
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{ |
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lsr |= UART_LSR_TEMT | UART_LSR_THRE; |
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canonical_terminal_t::write(val); |
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} |
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bool ns16550_t::load(reg_t addr, size_t len, uint8_t* bytes) |
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{ |
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uint8_t val; |
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bool ret = true, update = false; |
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if (reg_io_width != len) { |
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return false; |
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} |
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addr >>= reg_shift; |
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addr &= 7; |
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switch (addr) { |
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case UART_RX: |
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if (lcr & UART_LCR_DLAB) { |
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val = dll; |
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} else { |
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val = rx_byte(); |
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} |
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update = true; |
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break; |
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case UART_IER: |
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if (lcr & UART_LCR_DLAB) { |
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val = dlm; |
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} else { |
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val = ier; |
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} |
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break; |
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case UART_IIR: |
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val = iir | UART_IIR_TYPE_BITS; |
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break; |
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case UART_LCR: |
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val = lcr; |
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break; |
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case UART_MCR: |
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val = mcr; |
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break; |
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case UART_LSR: |
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val = lsr; |
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break; |
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case UART_MSR: |
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val = msr; |
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break; |
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case UART_SCR: |
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val = scr; |
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break; |
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default: |
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ret = false; |
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break; |
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}; |
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if (ret) { |
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bytes[0] = val; |
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} |
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if (update) { |
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update_interrupt(); |
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} |
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return ret; |
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} |
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bool ns16550_t::store(reg_t addr, size_t len, const uint8_t* bytes) |
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{ |
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uint8_t val; |
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bool ret = true, update = false; |
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if (reg_io_width != len) { |
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return false; |
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} |
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addr >>= reg_shift; |
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addr &= 7; |
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val = bytes[0]; |
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switch (addr) { |
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case UART_TX: |
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update = true; |
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if (lcr & UART_LCR_DLAB) { |
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dll = val; |
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break; |
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} |
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/* Loopback mode */ |
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if (mcr & UART_MCR_LOOP) { |
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if (rx_queue.size() < UART_QUEUE_SIZE) { |
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rx_queue.push(val); |
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lsr |= UART_LSR_DR; |
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} |
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break; |
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} |
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tx_byte(val); |
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break; |
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case UART_IER: |
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if (!(lcr & UART_LCR_DLAB)) { |
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ier = val & 0x0f; |
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} else { |
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dlm = val; |
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} |
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update = true; |
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break; |
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case UART_FCR: |
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fcr = val; |
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update = true; |
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break; |
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case UART_LCR: |
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lcr = val; |
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update = true; |
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break; |
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case UART_MCR: |
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mcr = val; |
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update = true; |
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break; |
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case UART_LSR: |
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/* Factory test */ |
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break; |
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case UART_MSR: |
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/* Not used */ |
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break; |
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case UART_SCR: |
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scr = val; |
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break; |
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default: |
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ret = false; |
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break; |
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}; |
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if (update) { |
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update_interrupt(); |
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} |
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return ret; |
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} |
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void ns16550_t::tick(void) |
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{ |
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int rc; |
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if (!(fcr & UART_FCR_ENABLE_FIFO) || |
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(mcr & UART_MCR_LOOP) || |
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(UART_QUEUE_SIZE <= rx_queue.size())) { |
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return; |
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} |
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rc = canonical_terminal_t::read(); |
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if (rc < 0) { |
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return; |
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} |
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rx_queue.push((uint8_t)rc); |
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lsr |= UART_LSR_DR; |
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update_interrupt(); |
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} |
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