From 17682e173d84b4d56defebb531409cac2acd5875 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 4 Jan 2026 22:46:11 -0800 Subject: [PATCH] Make all vector ALU instructions invoke VECTOR_END, dirtying VS dirty_vs_state is therefore no longer needed at the top in require_vector. Furthermore, the vstart write in VECTOR_END dirties VS, so dirty_vs_state is not needed. --- riscv/decode_macros.h | 2 -- riscv/insns/vcompress_vm.h | 3 ++- riscv/insns/vcpop_m.h | 2 ++ riscv/insns/vfbdot_vv.h | 2 ++ riscv/insns/vfirst_m.h | 2 ++ riscv/insns/vfmv_f_s.h | 2 +- riscv/insns/vfmv_s_f.h | 2 +- riscv/insns/vfqbdot_alt_vv.h | 2 ++ riscv/insns/vfqbdot_vv.h | 2 ++ riscv/insns/vfqldot_alt_vv.h | 2 ++ riscv/insns/vfqldot_vv.h | 2 ++ riscv/insns/vfwbdot_vv.h | 2 ++ riscv/insns/vfwldot_vv.h | 2 ++ riscv/insns/vid_v.h | 2 +- riscv/insns/viota_m.h | 1 + riscv/insns/vmsbf_m.h | 2 ++ riscv/insns/vmsif_m.h | 2 ++ riscv/insns/vmsof_m.h | 2 ++ riscv/insns/vmv_s_x.h | 2 +- riscv/insns/vmv_x_s.h | 2 +- riscv/insns/vmvnfr_v.h | 2 +- riscv/insns/vqbdots_vv.h | 2 ++ riscv/insns/vqbdotu_vv.h | 2 ++ riscv/insns/vqldots_vv.h | 2 ++ riscv/insns/vqldotu_vv.h | 2 ++ riscv/insns/vsetivli.h | 1 + riscv/insns/vsetvl.h | 1 + riscv/insns/vsetvli.h | 1 + riscv/v_ext_macros.h | 31 +++++++++++++++++-------------- riscv/zvk_ext_macros.h | 16 ++++++++-------- 30 files changed, 69 insertions(+), 31 deletions(-) diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h index 6f24799f..46cfee6a 100644 --- a/riscv/decode_macros.h +++ b/riscv/decode_macros.h @@ -173,14 +173,12 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) if (alu && !P.VU.vstart_alu) \ require(P.VU.vstart->read() == 0); \ WRITE_VSTATUS; \ - dirty_vs_state; \ } while (0); #define require_vector_novtype(is_log) \ do { \ require_vector_vs; \ if (is_log) \ WRITE_VSTATUS; \ - dirty_vs_state; \ } while (0); #define require_align(val, pos) require(is_aligned(val, pos)) #define require_noover(astart, asize, bstart, bsize) \ diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h index 6624d8b4..8754eb04 100644 --- a/riscv/insns/vcompress_vm.h +++ b/riscv/insns/vcompress_vm.h @@ -27,4 +27,5 @@ VI_GENERAL_LOOP_BASE ++pos; } -VI_LOOP_END_BASE; + +VI_LOOP_END; diff --git a/riscv/insns/vcpop_m.h b/riscv/insns/vcpop_m.h index 26a1276f..260f45d3 100644 --- a/riscv/insns/vcpop_m.h +++ b/riscv/insns/vcpop_m.h @@ -10,3 +10,5 @@ for (reg_t i=P.VU.vstart->read(); iread(); i < vl; ++i) { } } WRITE_RD(pos); + +VECTOR_END; diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 65a3cff3..f4e984e4 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -29,4 +29,4 @@ if (FLEN == 64) { WRITE_FRD(f32(vs2_0)); } -P.VU.vstart->write(0); +VECTOR_END; diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index 917948d7..11975f2c 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -21,4 +21,4 @@ if (vl > 0 && P.VU.vstart->read() < vl) { break; } } -P.VU.vstart->write(0); +VECTOR_END; diff --git a/riscv/insns/vfqbdot_alt_vv.h b/riscv/insns/vfqbdot_alt_vv.h index f1df781f..dcdcb119 100644 --- a/riscv/insns/vfqbdot_alt_vv.h +++ b/riscv/insns/vfqbdot_alt_vv.h @@ -15,3 +15,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vfqbdot_vv.h b/riscv/insns/vfqbdot_vv.h index fe3e6528..b4fdffe4 100644 --- a/riscv/insns/vfqbdot_vv.h +++ b/riscv/insns/vfqbdot_vv.h @@ -15,3 +15,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vfqldot_alt_vv.h b/riscv/insns/vfqldot_alt_vv.h index ea18828e..a2b7fd2c 100644 --- a/riscv/insns/vfqldot_alt_vv.h +++ b/riscv/insns/vfqldot_alt_vv.h @@ -15,3 +15,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vfqldot_vv.h b/riscv/insns/vfqldot_vv.h index b03ec29d..ca46d263 100644 --- a/riscv/insns/vfqldot_vv.h +++ b/riscv/insns/vfqldot_vv.h @@ -15,3 +15,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vfwbdot_vv.h b/riscv/insns/vfwbdot_vv.h index b8d35a75..47f7c9bf 100644 --- a/riscv/insns/vfwbdot_vv.h +++ b/riscv/insns/vfwbdot_vv.h @@ -13,3 +13,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vfwldot_vv.h b/riscv/insns/vfwldot_vv.h index 63a4e470..fe1cf096 100644 --- a/riscv/insns/vfwldot_vv.h +++ b/riscv/insns/vfwldot_vv.h @@ -13,3 +13,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index 510132de..ad7da219 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -25,4 +25,4 @@ for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl->read(); ++i) { } } -P.VU.vstart->write(0); +VECTOR_END; diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h index 00155db8..4a677693 100644 --- a/riscv/insns/viota_m.h +++ b/riscv/insns/viota_m.h @@ -45,3 +45,4 @@ for (reg_t i = 0; i < vl; ++i) { } } +VECTOR_END; diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 3f736e05..7c907a61 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -25,3 +25,5 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { P.VU.set_mask_elt(rd_num, i, res); } } + +VECTOR_END; diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index b029327e..7d98655f 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -26,3 +26,5 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { P.VU.set_mask_elt(rd_num, i, res); } } + +VECTOR_END; diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index 5753dbfb..caaff046 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -24,3 +24,5 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) { P.VU.set_mask_elt(rd_num, i, res); } } + +VECTOR_END; diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index 23a6b56d..bd848a83 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -26,4 +26,4 @@ if (vl > 0 && P.VU.vstart->read() < vl) { vl = 0; } -P.VU.vstart->write(0); +VECTOR_END; diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index 57a9e1a9..c28dbf4c 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -24,4 +24,4 @@ default: WRITE_RD(sext_xlen(res)); -P.VU.vstart->write(0); +VECTOR_END; diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index 9c528104..fa47bb6f 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -24,4 +24,4 @@ if (vd != vs2 && start < size) { } } -P.VU.vstart->write(0); +VECTOR_END; diff --git a/riscv/insns/vqbdots_vv.h b/riscv/insns/vqbdots_vv.h index 55c3dd28..de348358 100644 --- a/riscv/insns/vqbdots_vv.h +++ b/riscv/insns/vqbdots_vv.h @@ -21,3 +21,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vqbdotu_vv.h b/riscv/insns/vqbdotu_vv.h index a73d5687..8eee3a98 100644 --- a/riscv/insns/vqbdotu_vv.h +++ b/riscv/insns/vqbdotu_vv.h @@ -21,3 +21,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vqldots_vv.h b/riscv/insns/vqldots_vv.h index ce6376ac..bde22968 100644 --- a/riscv/insns/vqldots_vv.h +++ b/riscv/insns/vqldots_vv.h @@ -21,3 +21,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vqldotu_vv.h b/riscv/insns/vqldotu_vv.h index 2b674b13..cd3691a4 100644 --- a/riscv/insns/vqldotu_vv.h +++ b/riscv/insns/vqldotu_vv.h @@ -21,3 +21,5 @@ switch (P.VU.vsew) { } default: require(false); } + +VECTOR_END; diff --git a/riscv/insns/vsetivli.h b/riscv/insns/vsetivli.h index f880e96a..f30564fd 100644 --- a/riscv/insns/vsetivli.h +++ b/riscv/insns/vsetivli.h @@ -1,2 +1,3 @@ require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10())); +VECTOR_END; diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index 4d03542e..f18d5be7 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,3 @@ require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); +VECTOR_END; diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h index d1f43b57..140cc300 100644 --- a/riscv/insns/vsetvli.h +++ b/riscv/insns/vsetvli.h @@ -1,2 +1,3 @@ require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); +VECTOR_END; diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 853ea91f..5f1dd170 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -233,16 +233,19 @@ static inline bool is_overlapped_widen(const int astart, int asize, #define VI_LOOP_END_BASE \ } +#define VECTOR_END \ + P.VU.vstart->write(0) + #define VI_LOOP_END \ VI_LOOP_END_BASE \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LOOP_REDUCTION_END(x) \ } \ if (vl > 0) { \ vd_0_des = vd_0_res; \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LOOP_CARRY_BASE \ VI_GENERAL_LOOP_BASE \ @@ -253,7 +256,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, #define VI_LOOP_CARRY_END \ P.VU.set_mask_elt(insn.rd(), i, res); \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LOOP_WITH_CARRY_BASE \ VI_GENERAL_LOOP_BASE \ const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); \ @@ -274,7 +277,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, #define VI_LOOP_CMP_END \ P.VU.set_mask_elt(insn.rd(), i, res); \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LOOP_MASK(op) \ require(P.VU.vsew <= e64); \ @@ -285,7 +288,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, bool vs1 = P.VU.mask_elt(insn.rs1(), i); \ P.VU.set_mask_elt(insn.rd(), i, (op)); \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LOOP_NSHIFT_BASE \ VI_GENERAL_LOOP_BASE; \ @@ -1199,7 +1202,7 @@ VI_VX_ULOOP({ \ P.VU.elt(vd + fn * emul, vreg_inx, true) = val; \ } \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LDST_GET_INDEX(elt_width) \ reg_t index; \ @@ -1252,7 +1255,7 @@ VI_VX_ULOOP({ \ } \ } \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_ST(stride, offset, elt_width, is_mask_ldst) \ const reg_t nf = insn.v_nf() + 1; \ @@ -1270,7 +1273,7 @@ VI_VX_ULOOP({ \ baseAddr + (stride) + (offset) * sizeof(elt_width##_t), val); \ } \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_ST_INDEX(elt_width, is_seg) \ const reg_t nf = insn.v_nf() + 1; \ @@ -1306,7 +1309,7 @@ VI_VX_ULOOP({ \ } \ } \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_LDST_FF(elt_width) \ const reg_t nf = insn.v_nf() + 1; \ @@ -1355,7 +1358,7 @@ VI_VX_ULOOP({ \ auto val = MMU.load(baseAddr + i * sizeof(elt_width ## _t)); \ P.VU.elt(vd, i, true) = val; \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_ST_WHOLE \ require_vector_novtype(true); \ @@ -1369,7 +1372,7 @@ VI_VX_ULOOP({ \ auto val = P.VU.elt(vs3, i); \ MMU.store(baseAddr + i, val); \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_EXT_CHECK(div) \ require(insn.rd() != insn.rs2()); \ @@ -1478,11 +1481,11 @@ VI_VX_ULOOP({ \ #define VI_VFP_LOOP_END \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ #define VI_VFP_LOOP_REDUCTION_END(x) \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ if (vl > 0) { \ if (is_propagate && !is_active) { \ switch (x) { \ @@ -1544,7 +1547,7 @@ VI_VX_ULOOP({ \ break; \ }; \ } \ - P.VU.vstart->write(0); + VECTOR_END; #define VI_VFP_VV_LOOP(BODY16, BODY32, BODY64) \ VI_CHECK_SSS(true); \ diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h index e96e0a88..1ab43313 100644 --- a/riscv/zvk_ext_macros.h +++ b/riscv/zvk_ext_macros.h @@ -322,7 +322,7 @@ VV_VD_VS1_VS2_EGU32x4_PARAMS(vd_num, vs1_num, vs2_num, idx_eg); \ EG_BODY \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 32b*8 element groups available in the vector register @@ -377,7 +377,7 @@ VV_VD_VS1_VS2_EGU32x8_PARAMS(vd_num, vs1_num, vs2_num, idx_eg); \ EG_BODY \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 32b*4 element groups available in the vector register @@ -445,7 +445,7 @@ EG_BODY \ } \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 32b*4 element groups available in the vector register @@ -513,7 +513,7 @@ EG_BODY \ } \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 32b*4 element groups available in the vector registers @@ -560,7 +560,7 @@ VV_VD_VS2_EGU32x4_PARAMS(vd_num, vs2_num, idx_eg); \ EG_BODY \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 32b*4 element groups available in the vector registers @@ -616,7 +616,7 @@ EG_BODY \ } \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 32b*8 element groups available in the vector registers @@ -672,7 +672,7 @@ EG_BODY \ } \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0) // Processes all 64b*4 element groups available in the vector registers @@ -726,7 +726,7 @@ VV_VD_VS1_VS2_EGU64x4_PARAMS(vd_num, vs1_num, vs2_num, idx_eg); \ EG_BODY \ } \ - P.VU.vstart->write(0); \ + VECTOR_END; \ } while (0)