Make all vector ALU instructions invoke VECTOR_END, dirtying VS

dirty_vs_state is therefore no longer needed at the top in
require_vector.

Furthermore, the vstart write in VECTOR_END dirties VS, so
dirty_vs_state is not needed.

riscv/decode_macros.h

@@ -173,14 +173,12 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
     if (alu && !P.VU.vstart_alu) \
       require(P.VU.vstart->read() == 0); \
     WRITE_VSTATUS; \
-    dirty_vs_state; \
   } while (0);
 #define require_vector_novtype(is_log) \
   do { \
     require_vector_vs; \
     if (is_log) \
       WRITE_VSTATUS; \
-    dirty_vs_state; \
   } while (0);
 #define require_align(val, pos) require(is_aligned(val, pos))
 #define require_noover(astart, asize, bstart, bsize) \

riscv/insns/vcompress_vm.h

@@ -27,4 +27,5 @@ VI_GENERAL_LOOP_BASE
 
     ++pos;
   }
-VI_LOOP_END_BASE;
+
+VI_LOOP_END;

riscv/insns/vcpop_m.h

@@ -10,3 +10,5 @@ for (reg_t i=P.VU.vstart->read(); i<vl; ++i) {
   popcount += vs2_bit && (insn.v_vm() || P.VU.mask_elt(0, i));
 }
 WRITE_RD(popcount);
+
+VECTOR_END;

riscv/insns/vfbdot_vv.h

@@ -14,3 +14,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vfirst_m.h

@@ -14,3 +14,5 @@ for (reg_t i=P.VU.vstart->read(); i < vl; ++i) {
   }
 }
 WRITE_RD(pos);
+
+VECTOR_END;

riscv/insns/vfmv_f_s.h

@@ -29,4 +29,4 @@ if (FLEN == 64) {
   WRITE_FRD(f32(vs2_0));
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;

riscv/insns/vfmv_s_f.h

@@ -21,4 +21,4 @@ if (vl > 0 && P.VU.vstart->read() < vl) {
       break;
   }
 }
-P.VU.vstart->write(0);
+VECTOR_END;

riscv/insns/vfqbdot_alt_vv.h

@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vfqbdot_vv.h

@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vfqldot_alt_vv.h

@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vfqldot_vv.h

@@ -15,3 +15,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vfwbdot_vv.h

@@ -13,3 +13,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vfwldot_vv.h

@@ -13,3 +13,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vid_v.h

@@ -25,4 +25,4 @@ for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl->read(); ++i) {
   }
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;

riscv/insns/viota_m.h

@@ -45,3 +45,4 @@ for (reg_t i = 0; i < vl; ++i) {
   }
 }
 
+VECTOR_END;

riscv/insns/vmsbf_m.h

@@ -25,3 +25,5 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
     P.VU.set_mask_elt(rd_num, i, res);
   }
 }
+
+VECTOR_END;

riscv/insns/vmsif_m.h

@@ -26,3 +26,5 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
     P.VU.set_mask_elt(rd_num, i, res);
   }
 }
+
+VECTOR_END;

riscv/insns/vmsof_m.h

@@ -24,3 +24,5 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) {
     P.VU.set_mask_elt(rd_num, i, res);
   }
 }
+
+VECTOR_END;

riscv/insns/vmv_s_x.h

@@ -26,4 +26,4 @@ if (vl > 0 && P.VU.vstart->read() < vl) {
   vl = 0;
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;

riscv/insns/vmv_x_s.h

@@ -24,4 +24,4 @@ default:
 
 WRITE_RD(sext_xlen(res));
 
-P.VU.vstart->write(0);
+VECTOR_END;

riscv/insns/vmvnfr_v.h

@@ -24,4 +24,4 @@ if (vd != vs2 && start < size) {
   }
 }
 
-P.VU.vstart->write(0);
+VECTOR_END;

riscv/insns/vqbdots_vv.h

@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vqbdotu_vv.h

@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vqldots_vv.h

@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vqldotu_vv.h

@@ -21,3 +21,5 @@ switch (P.VU.vsew) {
   }
   default: require(false);
 }
+
+VECTOR_END;

riscv/insns/vsetivli.h

@@ -1,2 +1,3 @@
 require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10()));
+VECTOR_END;

riscv/insns/vsetvl.h

@@ -1,2 +1,3 @@
 require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2));
+VECTOR_END;

riscv/insns/vsetvli.h

@@ -1,2 +1,3 @@
 require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11()));
+VECTOR_END;

riscv/v_ext_macros.h

@@ -233,16 +233,19 @@ static inline bool is_overlapped_widen(const int astart, int asize,
 #define VI_LOOP_END_BASE \
  }
 
+#define VECTOR_END \
+  P.VU.vstart->write(0)
+
 #define VI_LOOP_END \
   VI_LOOP_END_BASE \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_LOOP_REDUCTION_END(x) \
   } \
   if (vl > 0) { \
     vd_0_des = vd_0_res; \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_LOOP_CARRY_BASE \
   VI_GENERAL_LOOP_BASE \
@@ -253,7 +256,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
 #define VI_LOOP_CARRY_END \
     P.VU.set_mask_elt(insn.rd(), i, res); \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 #define VI_LOOP_WITH_CARRY_BASE \
   VI_GENERAL_LOOP_BASE \
   const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); \
@@ -274,7 +277,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
 #define VI_LOOP_CMP_END \
     P.VU.set_mask_elt(insn.rd(), i, res); \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_LOOP_MASK(op) \
   require(P.VU.vsew <= e64); \
@@ -285,7 +288,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
     bool vs1 = P.VU.mask_elt(insn.rs1(), i); \
     P.VU.set_mask_elt(insn.rd(), i, (op)); \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_LOOP_NSHIFT_BASE \
   VI_GENERAL_LOOP_BASE; \
@@ -1199,7 +1202,7 @@ VI_VX_ULOOP({ \
       P.VU.elt<elt_width##_t>(vd + fn * emul, vreg_inx, true) = val; \
     } \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_LDST_GET_INDEX(elt_width) \
   reg_t index; \
@@ -1252,7 +1255,7 @@ VI_VX_ULOOP({ \
       } \
     } \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_ST(stride, offset, elt_width, is_mask_ldst) \
   const reg_t nf = insn.v_nf() + 1; \
@@ -1270,7 +1273,7 @@ VI_VX_ULOOP({ \
         baseAddr + (stride) + (offset) * sizeof(elt_width##_t), val); \
     } \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_ST_INDEX(elt_width, is_seg) \
   const reg_t nf = insn.v_nf() + 1; \
@@ -1306,7 +1309,7 @@ VI_VX_ULOOP({ \
       } \
     } \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_LDST_FF(elt_width) \
   const reg_t nf = insn.v_nf() + 1; \
@@ -1355,7 +1358,7 @@ VI_VX_ULOOP({ \
     auto val = MMU.load<elt_width##_t>(baseAddr + i * sizeof(elt_width ## _t)); \
     P.VU.elt<elt_width ## _t>(vd, i, true) = val; \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_ST_WHOLE \
   require_vector_novtype(true); \
@@ -1369,7 +1372,7 @@ VI_VX_ULOOP({ \
     auto val = P.VU.elt<uint8_t>(vs3, i); \
     MMU.store<uint8_t>(baseAddr + i, val); \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_EXT_CHECK(div) \
   require(insn.rd() != insn.rs2()); \
@@ -1478,11 +1481,11 @@ VI_VX_ULOOP({ \
 
 #define VI_VFP_LOOP_END \
   } \
-  P.VU.vstart->write(0); \
+  VECTOR_END; \
 
 #define VI_VFP_LOOP_REDUCTION_END(x) \
   } \
-  P.VU.vstart->write(0); \
+  VECTOR_END; \
   if (vl > 0) { \
     if (is_propagate && !is_active) { \
       switch (x) { \
@@ -1544,7 +1547,7 @@ VI_VX_ULOOP({ \
       break; \
     }; \
   } \
-  P.VU.vstart->write(0);
+  VECTOR_END;
 
 #define VI_VFP_VV_LOOP(BODY16, BODY32, BODY64) \
   VI_CHECK_SSS(true); \

riscv/zvk_ext_macros.h

@@ -322,7 +322,7 @@
       VV_VD_VS1_VS2_EGU32x4_PARAMS(vd_num, vs1_num, vs2_num, idx_eg); \
       EG_BODY \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 32b*8 element groups available in the vector register
@@ -377,7 +377,7 @@
       VV_VD_VS1_VS2_EGU32x8_PARAMS(vd_num, vs1_num, vs2_num, idx_eg); \
       EG_BODY \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 32b*4 element groups available in the vector register
@@ -445,7 +445,7 @@
         EG_BODY \
       } \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 32b*4 element groups available in the vector register
@@ -513,7 +513,7 @@
         EG_BODY \
       } \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 32b*4 element groups available in the vector registers
@@ -560,7 +560,7 @@
       VV_VD_VS2_EGU32x4_PARAMS(vd_num, vs2_num, idx_eg); \
       EG_BODY \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 32b*4 element groups available in the vector registers
@@ -616,7 +616,7 @@
         EG_BODY \
       } \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 32b*8 element groups available in the vector registers
@@ -672,7 +672,7 @@
         EG_BODY \
       } \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)
 
 // Processes all 64b*4 element groups available in the vector registers
@@ -726,7 +726,7 @@
       VV_VD_VS1_VS2_EGU64x4_PARAMS(vd_num, vs1_num, vs2_num, idx_eg); \
       EG_BODY \
     } \
-    P.VU.vstart->write(0); \
+    VECTOR_END; \
   } while (0)