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@ -3,17 +3,21 @@ |
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#include "spike/encoding.h" |
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// These are implementation-specific addresses in the Debug Module |
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#define HALTED 0x100 |
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#define GOING 0x104 |
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#define RESUMING 0x108 |
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#define EXCEPTION 0x10C |
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#define DEBUG_ROM_HALTED 0x100 |
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#define DEBUG_ROM_GOING 0x104 |
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#define DEBUG_ROM_RESUMING 0x108 |
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#define DEBUG_ROM_EXCEPTION 0x10C |
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// Region of memory where each hart has 1 |
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// byte to read. |
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#define FLAGS 0x400 |
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#define FLAG_GO 0 |
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#define FLAG_RESUME 1 |
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#define DEBUG_ROM_FLAGS 0x400 |
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#define DEBUG_ROM_FLAG_GO 0 |
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#define DEBUG_ROM_FLAG_RESUME 1 |
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// These needs to match the link.ld |
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#define DEBUG_ROM_WHERETO 0x300 |
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#define DEBUG_ROM_ENTRY 0x800 |
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.option norvc |
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.global entry |
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.global exception |
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@ -41,30 +45,30 @@ _entry: |
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// us to do, or whether we should resume. |
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entry_loop: |
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csrr s0, CSR_MHARTID |
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sw s0, HALTED(zero) |
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lbu s0, FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. |
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andi s0, s0, (1 << FLAG_GO) |
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sw s0, DEBUG_ROM_HALTED(zero) |
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lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. |
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andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) |
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bnez s0, going |
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csrr s0, CSR_MHARTID |
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lbu s0, FLAGS(s0) // multiple harts can resume here |
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andi s0, s0, (1 << FLAG_RESUME) |
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lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here |
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andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME) |
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bnez s0, resume |
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jal zero, entry_loop |
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_exception: |
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sw zero, EXCEPTION(zero) // Let debug module know you got an exception. |
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sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. |
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ebreak |
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going: |
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csrr s0, CSR_DSCRATCH // Restore s0 here |
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sw zero, GOING(zero) // When debug module sees this write, the GO flag is reset. |
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sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. |
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jalr zero, zero, %lo(whereto) // Rocket-Chip has a specific hack which is that jalr in |
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// Debug Mode will flush the I-Cache. We need that so that the |
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// remainder of the variable instructions will be what Debug Module |
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// intends. |
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_resume: |
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csrr s0, CSR_MHARTID |
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sw s0, RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. |
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sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. |
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csrr s0, CSR_DSCRATCH // Restore s0 |
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dret |
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