add comment to spike.cc and clean up code in sim.cc

riscv/sim.cc

@@ -106,7 +106,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
                                       log_file.get(), sout_));
       harts[cfg->hartids[i]] = procs[i];
     }
-    for (auto& x : this->mems) {
+    for (auto& x : mems) {
       bus.add_device(x.first, x.second);
     }
     for (auto& pair : harts) {
@@ -254,15 +254,15 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
                           dtb_discovery_plugin_device_factories.end());
 
     //Remove default memories and use dtb discovered memories
-    this->mems.clear();
-    dtb_discovery::discover_memory_from_dtb(fdt, this->mems);
+    mems.clear();
+    dtb_discovery::discover_memory_from_dtb(fdt, mems);
   }
   //clint, plic, ns16550 are always discovered via dtb, independently from the --dtb_discovery flag
   device_factories.insert(device_factories.end(),
                           plugin_device_factories.begin(),
                           plugin_device_factories.end());
 
-  for (auto& x : this->mems)
+  for (auto& x : mems)
   {
       bus.add_device(x.first, x.second);
   }

spike_main/spike.cc

@@ -47,7 +47,7 @@ static void help(int exit_code = 1)
   fprintf(stderr, "  --pmpgranularity=<n>  PMP Granularity in bytes [default 4]\n");
   fprintf(stderr, "  --priv=<m|mu|msu>     RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV);
   fprintf(stderr, "  --pc=<address>        Override ELF entry point\n");
-  fprintf(stderr, "  --pcs=<H:A,...>       Override start PC for specific harts\n");
+  fprintf(stderr, "  --pcs=<H:A,...>       Override start PC for specific hart\n"); //This will bypass the built-in boot ROM
   fprintf(stderr, "  --hartids=<a,b,...>   Explicitly specify hartids, default is 0,1,...\n");
   fprintf(stderr, "  --ic=<S>:<W>:<B>      Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>        W ways, and B-byte blocks (with S and\n");