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ci: auto-generate per extension snippy tests 

This way adding new extension tests is as easy as adding 1 line script
call and it is much harder to leave some instruction untested
pull/2169/head
Alexander Romanov 4 months ago
parent
6392b9e60d
commit
0f289394f3
13 changed files with 297 additions and 1190 deletions
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  1. 18
      ci-tests/generate-snippy-test.sh
  2. 39
      ci-tests/generate-snippy-tests.sh
  3. 37
      ci-tests/run-snippy-test.sh
  4. 112
      ci-tests/run-snippy-tests.sh
  5. 67
      ci-tests/snippy-tests/atomic.yaml
  6. 57
      ci-tests/snippy-tests/basic.yaml
  7. 76
      ci-tests/snippy-tests/compressed.yaml
  8. 109
      ci-tests/snippy-tests/double-fp.yaml
  9. 137
      ci-tests/snippy-tests/generate-snippy-test.sh
  10. 22
      ci-tests/snippy-tests/sections.yaml
  11. 84
      ci-tests/snippy-tests/single-fp.yaml
  12. 717
      ci-tests/snippy-tests/vector.yaml
  13. 12
      ci-tests/test-spike

18
ci-tests/generate-snippy-test.sh
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@ -1,18 +0,0 @@
#!/usr/bin/env bash
set -e -x
CONFIG="$1"
RESULT="$2"
BOOTCODE="$3"
TRIPLE="$4"
ARCH="$5"
ABI="$6"
CONFIGDIR=$(dirname "$CONFIG")
base=$(basename "$CONFIG" .yaml)
elf="$base".elf
./llvm-snippy "$CONFIG" -o "$elf" --seed 1 -mtriple="$TRIPLE" -march="$ARCH" -riscv-disable-misaligned-access
riscv64-linux-gnu-gcc -O0 -march="$ARCH" -mabi="$ABI" -T "$elf".ld -T "$CONFIGDIR"/linker-entry.ld "$elf" "$BOOTCODE" -nostdlib -static -o "$RESULT" -Wl,--build-id=none

39
ci-tests/generate-snippy-tests.sh
View File

@ -1,39 +0,0 @@
#!/usr/bin/env bash
set -e -x
WORKDIR="$1"
CONFIGDIR="$2"
RESULTDIR="$WORKDIR"/snippy-tests
mkdir -p "$WORKDIR"
mkdir -p "$RESULTDIR"
generate_script=`git rev-parse --show-toplevel`/ci-tests/generate-snippy-test.sh
"$generate_script" "$CONFIGDIR"/basic.yaml "$RESULTDIR"/basic64.elf \
"$CONFIGDIR"/boot-code.s riscv64-unknown-elf rv64i_zicsr lp64
"$generate_script" "$CONFIGDIR"/basic.yaml "$RESULTDIR"/basic32.elf \
"$CONFIGDIR"/boot-code.s riscv32-unknown-elf rv32i_zicsr ilp32
"$generate_script" "$CONFIGDIR"/compressed.yaml "$RESULTDIR"/compressed64.elf \
"$CONFIGDIR"/boot-code.s riscv64-unknown-elf rv64ic_zicsr lp64
"$generate_script" "$CONFIGDIR"/compressed.yaml "$RESULTDIR"/compressed32.elf \
"$CONFIGDIR"/boot-code.s riscv32-unknown-elf rv32ic_zicsr ilp32
"$generate_script" "$CONFIGDIR"/double-fp.yaml "$RESULTDIR"/double64.elf \
"$CONFIGDIR"/boot-code-f.s riscv64-unknown-elf rv64ifd_zicsr lp64d
"$generate_script" "$CONFIGDIR"/double-fp.yaml "$RESULTDIR"/double32.elf \
"$CONFIGDIR"/boot-code-f.s riscv32-unknown-elf rv32ifd_zicsr ilp32d
"$generate_script" "$CONFIGDIR"/single-fp.yaml "$RESULTDIR"/float64.elf \
"$CONFIGDIR"/boot-code-f.s riscv64-unknown-elf rv64if_zicsr lp64f
"$generate_script" "$CONFIGDIR"/single-fp.yaml "$RESULTDIR"/float32.elf \
"$CONFIGDIR"/boot-code-f.s riscv32-unknown-elf rv32if_zicsr ilp32f
"$generate_script" "$CONFIGDIR"/vector.yaml "$RESULTDIR"/vector64.elf \
"$CONFIGDIR"/boot-code-vf.s riscv64-unknown-elf rv64gcv lp64d

37
ci-tests/run-snippy-test.sh
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@ -0,0 +1,37 @@
#!/usr/bin/env bash
set -e -x
set -o pipefail
ROOT="$1"
NUMINSTRS="$2"
BOOTCODE="$3"
TRIPLE="$4"
ARCH="$5"
EXTENSIONS="$6"
ABI="$7"
SPIKE_PATH="$8"
CONFIGDIR="$ROOT"/ci-tests/snippy-tests
CONFIG="test-$ARCH-$ABI.yaml"
base=$(basename "$CONFIG" .yaml)
testfile="$base".elf
tmpelf="$base".tmp.elf
# exclude C_JR and C_JALR and some othe compressed opcodes as snippy has issues with them
# exclude EBREAK/ECALL as we want non-privileged instructions
# exclude lr.rl and sc.aq as they don't make sense
"$CONFIGDIR"/generate-snippy-test.sh --march "$ARCH" --mtriple "$TRIPLE" --extensions "$EXTENSIONS" --num-instrs $NUMINSTRS --ignore-opcode-regex "C_JR|C_JALR|EBREAK|ECALL|C_.*(SP|HINT|UNIMP).*|LR_.*_RL|SC_.*_AQ" > "$CONFIG"
llvm-snippy "$CONFIG" -o "$tmpelf" --seed 1 -riscv-disable-misaligned-access --layout-include-dir "$ROOT"/ci-tests/snippy-tests
riscv64-linux-gnu-gcc -O0 -march="$ARCH" -mabi="$ABI" -T "$tmpelf".ld -T "$CONFIGDIR"/linker-entry.ld "$tmpelf" "$BOOTCODE" -nostdlib -static -o "$testfile" -Wl,--build-id=none
error=0
if ! timeout --foreground 60s "$SPIKE_PATH" -l --log-commits --isa "$ARCH" "$testfile"
then
echo "TIMEOUT: $testfile"
error=1
else
echo "SUCCESS: $testfile"
fi
exit $error

112
ci-tests/run-snippy-tests.sh
View File

@ -1,19 +1,97 @@
#!/usr/bin/env bash
set -x
TESTDIR="$1"
SPIKE_PATH="$2"
error=0
for testfile in "$TESTDIR"/*; do
bitness=$(basename "$testfile" .elf | grep -o "[0-9]\+")
if ! timeout --foreground 5s "$SPIKE_PATH" -l --log-commits --isa rv"$bitness"ifdcv_zicsr "$testfile"
then
echo "TIMEOUT: $testfile"
error=1
else
echo "SUCCESS: $testfile"
fi
done
exit $error
set -e -x
WORKDIR="$1"
CONFIGDIR="$2"
SPIKE_PATH="$3"
RESULTDIR="$WORKDIR"/snippy-tests
mkdir -p "$WORKDIR"
mkdir -p "$RESULTDIR"
ROOT=`git rev-parse --show-toplevel`
run_test_script="$ROOT"/ci-tests/run-snippy-test.sh
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv64 rv64i_zicsr_zifencei "i" lp64 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv32 rv32i_zicsr_zifencei "i" ilp32 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv64 rv64ic_zicsr_zifencei "c - d" lp64 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv32 rv32ic_zicsr_zifencei "c - d" ilp32 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifd_zicsr_zifencei "d - c - zfa - zvfh" lp64d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifd_zicsr_zifencei "d - c - zfa - zvfh" ilp32d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64if_zicsr_zifencei "f - c" lp64f "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32if_zicsr_zifencei "f - c" ilp32f "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifc_zicsr_zifencei "f" lp64f "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifc_zicsr_zifencei "f" ilp32f "$SPIKE_PATH"
"$run_test_script" "$ROOT" 2000 \
"$CONFIGDIR"/boot-code-vf.s riscv64 rv64gcv_zfa_zvfh "v" lp64d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifc_zicsr_zifencei_zfhmin "f + zfhmin - d" lp64f "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifc_zicsr_zifencei_zfhmin "f + zfhmin - d" ilp32f "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifdc_zicsr_zifencei "d - zfa - zvfh" lp64d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifdc_zicsr_zifencei "d - zfa - zvfh" ilp32d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifdc_zicsr_zifencei_zfhmin "d - zfa + zfhmin" lp64d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifdc_zicsr_zifencei_zfhmin "d - zfa + zfhmin" ilp32d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifdc_zicsr_zifencei_zfh_zfa "d + zfh" lp64d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifdc_zicsr_zifencei_zfh_zfa "d + zfh" ilp32d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv64 rv64i_zicsr_zifencei_zca "zca" lp64 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv32 rv32i_zicsr_zifencei_zca "zca" ilp32 "$SPIKE_PATH"
# rv32-only zcf
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32if_zicsr_zifencei_zca_zcf "zcf" ilp32f "$SPIKE_PATH"
# zcd
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv64 rv64ifd_zicsr_zifencei_zca_zcd "zca + zcd - zfa - zfh" lp64d "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code-f.s riscv32 rv32ifd_zicsr_zifencei_zca_zcd "zca + zcd - zfa - zfh" ilp32d "$SPIKE_PATH"
# zcb
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv64 rv64i_zicsr_zifencei_zca_zcb_zmmul_zba_zbb "zca + zcb" lp64 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv32 rv32i_zicsr_zifencei_zca_zcb_zmmul_zba_zbb "zca + zcb" ilp32 "$SPIKE_PATH"
# zawrs
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv64 rv64ia_zicsr_zifencei_zawrs "zawrs + zalrsc" lp64 "$SPIKE_PATH"
"$run_test_script" "$ROOT" 3000 \
"$CONFIGDIR"/boot-code.s riscv32 rv32ia_zicsr_zifencei_zawrs "zawrs + zalrsc" ilp32 "$SPIKE_PATH"

67
ci-tests/snippy-tests/atomic.yaml
View File

@ -1,67 +0,0 @@
options:
mattr: +a
num-instrs: 1000
entry-point: SNIPPY_ENTRY
model-plugin: None
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw
histogram:
- ["AMOADD_[WD].*", 1.0]
- ["AMOAND_[WD].*", 1.0]
- ["AMOMAXU_[WD].*", 1.0]
- ["AMOMAX_[WD].*", 1.0]
- ["AMOMINU_[WD].*", 1.0]
- ["AMOMIN_[WD].*", 1.0]
- ["AMOOR_[WD].*", 1.0]
- ["AMOSWAP_[WD].*", 1.0]
- ["AMOXOR_[WD].*", 1.0]
- ["ADD", 1.0]
- ["ADDI", 1.0]
- ["AND", 1.0]
- ["ANDI", 1.0]
- ["AUIPC", 1.0]
- ["BEQ", 3.0]
- ["BGE", 3.0]
- ["BGEU", 3.0]
- ["BLT", 3.0]
- ["BLTU", 3.0]
- ["BNE", 3.0]
- ["L[BHWD][U]?", 1.0]
- ["S[BHWD]", 1.0]
- ["LUI", 1.0]
- ["OR", 1.0]
- ["ORI", 1.0]
- ["SLL", 1.0]
- ["SLLI", 1.0]
- ["SLT", 1.0]
- ["SLTI", 1.0]
- ["SLTIU", 1.0]
- ["SLTU", 1.0]
- ["SRA", 1.0]
- ["SRAI", 1.0]
- ["SRL", 1.0]
- ["SRLI", 1.0]
- ["SUB", 1.0]
- ["XOR", 1.0]
- ["XORI", 1.0]

57
ci-tests/snippy-tests/basic.yaml
View File

@ -1,57 +0,0 @@
options:
num-instrs: 1000
entry-point: SNIPPY_ENTRY
model-plugin: None
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw
histogram:
- ["ADD", 1.0]
- ["ADDI", 1.0]
- ["AND", 1.0]
- ["ANDI", 1.0]
- ["AUIPC", 1.0]
- ["BEQ", 3.0]
- ["BGE", 3.0]
- ["BGEU", 3.0]
- ["BLT", 3.0]
- ["BLTU", 3.0]
- ["BNE", 3.0]
- ["L[BHWD][U]?", 1.0]
- ["S[BHWD]", 1.0]
- ["LUI", 1.0]
- ["OR", 1.0]
- ["ORI", 1.0]
- ["SLL", 1.0]
- ["SLLI", 1.0]
- ["SLT", 1.0]
- ["SLTI", 1.0]
- ["SLTIU", 1.0]
- ["SLTU", 1.0]
- ["SRA", 1.0]
- ["SRAI", 1.0]
- ["SRL", 1.0]
- ["SRLI", 1.0]
- ["SUB", 1.0]
- ["XOR", 1.0]
- ["XORI", 1.0]

76
ci-tests/snippy-tests/compressed.yaml
View File

@ -1,76 +0,0 @@
options:
mattr: +c
num-instrs: 1000
entry-point: SNIPPY_ENTRY
model-plugin: None
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw
histogram:
- ["C_ADD.*", 1.0]
- ["C_AND", 1.0]
- ["C_ANDI", 1.0]
- ["C_BEQZ", 5.0]
- ["C_BNEZ", 5.0]
- ["C_L[WD]", 1.0]
- ["C_S[WD]", 1.0]
- ["C_LI", 1.0]
- ["C_LUI", 1.0]
- ["C_MV", 1.0]
- ["C_OR", 1.0]
- ["C_SLLI", 1.0]
- ["C_SRAI", 1.0]
- ["C_SRLI", 1.0]
- ["C_SUB[W]?", 1.0]
- ["C_XOR", 1.0]
- ["ADD", 1.0]
- ["ADDI", 1.0]
- ["AND", 1.0]
- ["ANDI", 1.0]
- ["AUIPC", 1.0]
- ["BEQ", 3.0]
- ["BGE", 3.0]
- ["BGEU", 3.0]
- ["BLT", 3.0]
- ["BLTU", 3.0]
- ["BNE", 3.0]
- ["L[BHWD][U]?", 1.0]
- ["S[BHWD]", 1.0]
- ["LUI", 1.0]
- ["OR", 1.0]
- ["ORI", 1.0]
- ["SB", 1.0]
- ["SH", 1.0]
- ["SLL", 1.0]
- ["SLLI", 1.0]
- ["SLT", 1.0]
- ["SLTI", 1.0]
- ["SLTIU", 1.0]
- ["SLTU", 1.0]
- ["SRA", 1.0]
- ["SRAI", 1.0]
- ["SRL", 1.0]
- ["SRLI", 1.0]
- ["SUB", 1.0]
- ["XOR", 1.0]
- ["XORI", 1.0]

109
ci-tests/snippy-tests/double-fp.yaml
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@ -1,109 +0,0 @@
options:
mattr: +f,+d
num-instrs: 1000
entry-point: SNIPPY_ENTRY
model-plugin: None
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw
histogram:
- ["FMADD_S", 1.0]
- ["FMSUB_S", 1.0]
- ["FNMSUB_S", 1.0]
- ["FNMADD_S", 1.0]
- ["FADD_S", 1.0]
- ["FSUB_S", 1.0]
- ["FMUL_S", 1.0]
- ["FDIV_S", 1.0]
- ["FSQRT_S", 1.0]
- ["FSGNJ_S", 1.0]
- ["FSGNJN_S", 1.0]
- ["FSGNJX_S", 1.0]
- ["FMIN_S", 1.0]
- ["FMAX_S", 1.0]
- ["FCVT_[WL]_S", 1.0]
- ["FCVT_[WL]U_S", 1.0]
- ["FEQ_S", 1.0]
- ["FLT_S", 1.0]
- ["FLE_S", 1.0]
- ["FCLASS_S", 1.0]
- ["FCVT_S_[WL]", 1.0]
- ["FCVT_S_[WL]U", 1.0]
- ["FMV_.*", 1.0]
- ["FL[WD]", 1.0]
- ["FS[WD]", 1.0]
- ["FMADD_D", 1.0]
- ["FMSUB_D", 1.0]
- ["FNMSUB_D", 1.0]
- ["FNMADD_D", 1.0]
- ["FADD_D", 1.0]
- ["FSUB_D", 1.0]
- ["FMUL_D", 1.0]
- ["FDIV_D", 1.0]
- ["FSQRT_D", 1.0]
- ["FSGNJ_D", 1.0]
- ["FSGNJN_D", 1.0]
- ["FSGNJX_D", 1.0]
- ["FMIN_D", 1.0]
- ["FMAX_D", 1.0]
- ["FCVT_[WL]_D", 1.0]
- ["FCVT_[WL]U_D", 1.0]
- ["FCVT_D_[WL]", 1.0]
- ["FCVT_D_[WL]U", 1.0]
- ["FEQ_D", 1.0]
- ["FLT_D", 1.0]
- ["FLE_D", 1.0]
- ["FCLASS_D", 1.0]
- ["FCVT_S_D", 1.0]
- ["FCVT_D_S", 1.0]
- ["FL[WD]", 1.0]
- ["FS[WD]", 1.0]
- ["ADD", 1.0]
- ["ADDI", 1.0]
- ["AND", 1.0]
- ["ANDI", 1.0]
- ["AUIPC", 1.0]
- ["BEQ", 3.0]
- ["BGE", 3.0]
- ["BGEU", 3.0]
- ["BLT", 3.0]
- ["BLTU", 3.0]
- ["BNE", 3.0]
- ["L[BHWD][U]?", 1.0]
- ["S[BHWD]", 1.0]
- ["LUI", 1.0]
- ["OR", 1.0]
- ["ORI", 1.0]
- ["SLL", 1.0]
- ["SLLI", 1.0]
- ["SLT", 1.0]
- ["SLTI", 1.0]
- ["SLTIU", 1.0]
- ["SLTU", 1.0]
- ["SRA", 1.0]
- ["SRAI", 1.0]
- ["SRL", 1.0]
- ["SRLI", 1.0]
- ["SUB", 1.0]
- ["XOR", 1.0]
- ["XORI", 1.0]

137
ci-tests/snippy-tests/generate-snippy-test.sh
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@ -0,0 +1,137 @@
#!/usr/bin/env bash
set -euo pipefail
args=("$@")
march=
mtriple=
extensions=
ignore_regex='^$'
includes=("./sections.yaml")
num_instrs=1000
usage() {
{
echo "isa-tests-gen.sh [options]"
echo " --march : Target architecture [required]"
echo " --mtriple : Target triple"
echo " --extensions : Target extensions string"
echo " --include : Additional include"
echo " --num-instrs : Number of instructions to generate (default: $num_instrs)"
echo " --ignore-opcode-regex : Regex to filter out opcodes"
echo " -h, --help : Print this help message"
} >&2
}
while [[ $# -gt 0 ]]; do
case $1 in
--march)
shift
march=$1
shift
;;
--mtriple)
shift
mtriple=$1
shift
;;
--extensions)
shift
extensions="$1"
shift
;;
--include)
shift
includes+=("$1")
shift
;;
--num-instrs)
shift
num_instrs="$1"
shift
;;
--ignore-opcode-regex)
shift
ignore_regex="$1"
shift
;;
-h | --help)
usage
exit 0
;;
*)
usage
exit 1
;;
esac
done
declare -a ie_args
case $mtriple in
riscv32)
ie_args+=("-arch=riscv" "--rv32" "-riscv-ext" "$extensions")
;;
riscv64)
ie_args+=("-arch=riscv" "--rv64" "-riscv-ext" "$extensions")
;;
*)
echo "error: Unrecognized --mtriple" >&2
usage
exit 1
;;
esac
ie_args+=("--disable-pseudo")
if [[ -z "$march" ]]; then
echo "error: --march hasn't been specified" >&2
exit 1
fi
if ! [ -x "$(command -v llvm-ie)" ]; then
echo "error: 'llvm-ie' is not in PATH" >&2
exit 1
fi
mapfile -t opcodes < <(llvm-ie "${ie_args[@]}")
filtered_opcodes=()
for opc in "${opcodes[@]}"; do
if [[ ! "$opc" =~ $ignore_regex ]]; then
filtered_opcodes+=("$opc")
fi
done
if [[ ${#filtered_opcodes[@]} -eq 0 ]]; then
echo "error: No opcodes matched" >&2
exit 1
fi
echo "# generated with" "$(basename "$0"), to regenerate run:"
printf "# %s" "$(basename "$0")"
for arg in "${args[@]}"; do
printf " %q" "$arg"
done
printf "\n"
echo "include:"
for inc in "${includes[@]}"; do
echo " - \"$inc\""
done
cat <<EOF
options:
march: ${march}
mtriple: ${mtriple}
num-instrs: ${num_instrs}
model-plugin: None
entry-point: SNIPPY_ENTRY
riscv-init-fregs-from-memory: true
histogram:
EOF
for opc in "${filtered_opcodes[@]}"; do
echo " - [$opc, 1.0]"
done
printf "\n"

22
ci-tests/snippy-tests/sections.yaml
View File

@ -0,0 +1,22 @@
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw

84
ci-tests/snippy-tests/single-fp.yaml
View File

@ -1,84 +0,0 @@
options:
mattr: +f
num-instrs: 1000
entry-point: SNIPPY_ENTRY
model-plugin: None
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw
histogram:
- ["FMADD_S", 1.0]
- ["FMSUB_S", 1.0]
- ["FNMSUB_S", 1.0]
- ["FNMADD_S", 1.0]
- ["FADD_S", 1.0]
- ["FSUB_S", 1.0]
- ["FMUL_S", 1.0]
- ["FDIV_S", 1.0]
- ["FSQRT_S", 1.0]
- ["FSGNJ_S", 1.0]
- ["FSGNJN_S", 1.0]
- ["FSGNJX_S", 1.0]
- ["FMIN_S", 1.0]
- ["FMAX_S", 1.0]
- ["FMV_X_[WL]", 1.0]
- ["FEQ_S", 1.0]
- ["FLT_S", 1.0]
- ["FLE_S", 1.0]
- ["FCLASS_S", 1.0]
- ["FCVT_S_[WL]", 1.0]
- ["FCVT_S_[WL]U", 1.0]
- ["FCVT_[WL]U_S", 1.0]
- ["FCVT_[WL]_S", 1.0]
- ["FMV_[WL]_X", 1.0]
- ["FL[WD]", 1.0]
- ["FS[WD]", 1.0]
- ["ADD", 1.0]
- ["ADDI", 1.0]
- ["AND", 1.0]
- ["ANDI", 1.0]
- ["AUIPC", 1.0]
- ["BEQ", 3.0]
- ["BGE", 3.0]
- ["BGEU", 3.0]
- ["BLT", 3.0]
- ["BLTU", 3.0]
- ["BNE", 3.0]
- ["L[BHWD][U]?", 1.0]
- ["S[BHWD]", 1.0]
- ["LUI", 1.0]
- ["OR", 1.0]
- ["ORI", 1.0]
- ["SLL", 1.0]
- ["SLLI", 1.0]
- ["SLT", 1.0]
- ["SLTI", 1.0]
- ["SLTIU", 1.0]
- ["SLTU", 1.0]
- ["SRA", 1.0]
- ["SRAI", 1.0]
- ["SRL", 1.0]
- ["SRLI", 1.0]
- ["SUB", 1.0]
- ["XOR", 1.0]
- ["XORI", 1.0]

717
ci-tests/snippy-tests/vector.yaml
View File

@ -1,717 +0,0 @@
options:
num-instrs: 2000
entry-point: SNIPPY_ENTRY
model-plugin: None
sections:
- name: 0
VMA: 0x80000000
SIZE: 0x10000
LMA: 0x80000000
ACCESS: r
- name: 1
VMA: 0x80020000
SIZE: 0x20000
LMA: 0x80020000
ACCESS: rx
- name: 2
VMA: 0x80040000
SIZE: 0x10000
LMA: 0x80040000
ACCESS: rw
- name: stack
VMA: 0x80050000
SIZE: 0x10000
LMA: 0x80050000
ACCESS: rw
riscv-vector-unit:
mode-change-bias:
P: 0.2
mode-distribution:
VM:
- [all_ones, 2.0]
- [any_legal, 1.0]
VL:
- [max_encodable, 2.0]
- [any_legal, 1.0]
VXRM:
rnu: 1.0
rne: 1.0
rdn: 1.0
ron: 1.0
VTYPE:
SEW:
sew_8: 1.0
sew_16: 1.0
sew_32: 1.0
sew_64: 1.0
LMUL:
m1: 1.0
m2: 1.0
m4: 1.0
m8: 1.0
mf2: 1.0
mf4: 1.0
mf8: 1.0
VMA:
mu: 1.0
ma: 1.0
VTA:
tu: 1.0
ta: 1.0
histogram:
- ["ADD", 1.0]
- ["ADDI", 1.0]
- ["AND", 1.0]
- ["ANDI", 1.0]
- ["AUIPC", 1.0]
- ["BEQ", 5.0]
- ["BGE", 5.0]
- ["BGEU", 5.0]
- ["BLT", 5.0]
- ["BLTU", 5.0]
- ["BNE", 5.0]
- ["L[BHWD][U]?", 5.0]
- ["S[BHWD]", 5.0]
- ["LUI", 1.0]
- ["OR", 1.0]
- ["ORI", 1.0]
- ["SLL", 1.0]
- ["SLLI", 1.0]
- ["SLT", 1.0]
- ["SLTI", 1.0]
- ["SLTIU", 1.0]
- ["SLTU", 1.0]
- ["SRA", 1.0]
- ["SRAI", 1.0]
- ["SRL", 1.0]
- ["SRLI", 1.0]
- ["SUB", 1.0]
- ["XOR", 1.0]
- ["XORI", 1.0]
- ["VAADDU_VV", 1.0]
- ["VAADDU_VX", 1.0]
- ["VAADD_VV", 1.0]
- ["VAADD_VX", 1.0]
- ["VADC_VIM", 1.0]
- ["VADC_VVM", 1.0]
- ["VADC_VXM", 1.0]
- ["VADD_VI", 1.0]
- ["VADD_VV", 1.0]
- ["VADD_VX", 1.0]
- ["VAND_VI", 1.0]
- ["VAND_VV", 1.0]
- ["VAND_VX", 1.0]
- ["VASUBU_VV", 1.0]
- ["VASUBU_VX", 1.0]
- ["VASUB_VV", 1.0]
- ["VASUB_VX", 1.0]
- ["VCOMPRESS_VM", 1.0]
- ["VCPOP_M", 1.0]
- ["VDIVU_VV", 1.0]
- ["VDIVU_VX", 1.0]
- ["VDIV_VV", 1.0]
- ["VDIV_VX", 1.0]
- ["VFADD_VF", 1.0]
- ["VFADD_VV", 1.0]
- ["VFCLASS_V", 1.0]
- ["VFCVT_F_XU_V", 1.0]
- ["VFCVT_F_X_V", 1.0]
- ["VFCVT_RTZ_XU_F_V", 1.0]
- ["VFCVT_RTZ_X_F_V", 1.0]
- ["VFCVT_XU_F_V", 1.0]
- ["VFCVT_X_F_V", 1.0]
- ["VFDIV_VF", 1.0]
- ["VFDIV_VV", 1.0]
- ["VFIRST_M", 1.0]
- ["VFMACC_VF", 1.0]
- ["VFMACC_VV", 1.0]
- ["VFMADD_VF", 1.0]
- ["VFMADD_VV", 1.0]
- ["VFMAX_VF", 1.0]
- ["VFMAX_VV", 1.0]
- ["VFMERGE_VFM", 1.0]
- ["VFMIN_VF", 1.0]
- ["VFMIN_VV", 1.0]
- ["VFMSAC_VF", 1.0]
- ["VFMSAC_VV", 1.0]
- ["VFMSUB_VF", 1.0]
- ["VFMSUB_VV", 1.0]
- ["VFMUL_VF", 1.0]
- ["VFMUL_VV", 1.0]
- ["VFMV_F_S", 1.0]
- ["VFMV_S_F", 1.0]
- ["VFMV_V_F", 1.0]
- ["VFNCVT_F_F_W", 1.0]
- ["VFNCVT_F_XU_W", 1.0]
- ["VFNCVT_F_X_W", 1.0]
- ["VFNCVT_ROD_F_F_W", 1.0]
- ["VFNCVT_RTZ_XU_F_W", 1.0]
- ["VFNCVT_RTZ_X_F_W", 1.0]
- ["VFNCVT_XU_F_W", 1.0]
- ["VFNCVT_X_F_W", 1.0]
- ["VFNMACC_VF", 1.0]
- ["VFNMACC_VV", 1.0]
- ["VFNMADD_VF", 1.0]
- ["VFNMADD_VV", 1.0]
- ["VFNMSAC_VF", 1.0]
- ["VFNMSAC_VV", 1.0]
- ["VFNMSUB_VF", 1.0]
- ["VFNMSUB_VV", 1.0]
- ["VFRDIV_VF", 1.0]
- ["VFREC7_V", 1.0]
- ["VFREDMAX_VS", 1.0]
- ["VFREDMIN_VS", 1.0]
- ["VFREDOSUM_VS", 1.0]
- ["VFREDUSUM_VS", 1.0]
- ["VFRSQRT7_V", 1.0]
- ["VFRSUB_VF", 1.0]
- ["VFSGNJN_VF", 1.0]
- ["VFSGNJN_VV", 1.0]
- ["VFSGNJX_VF", 1.0]
- ["VFSGNJX_VV", 1.0]
- ["VFSGNJ_VF", 1.0]
- ["VFSGNJ_VV", 1.0]
- ["VFSLIDE1DOWN_VF", 1.0]
- ["VFSLIDE1UP_VF", 1.0]
- ["VFSQRT_V", 1.0]
- ["VFSUB_VF", 1.0]
- ["VFSUB_VV", 1.0]
- ["VFWADD_VF", 1.0]
- ["VFWADD_VV", 1.0]
- ["VFWADD_WF", 1.0]
- ["VFWADD_WV", 1.0]
- ["VFWCVT_F_F_V", 1.0]
- ["VFWCVT_F_XU_V", 1.0]
- ["VFWCVT_F_X_V", 1.0]
- ["VFWCVT_RTZ_XU_F_V", 1.0]
- ["VFWCVT_RTZ_X_F_V", 1.0]
- ["VFWCVT_XU_F_V", 1.0]
- ["VFWCVT_X_F_V", 1.0]
- ["VFWMACC_VF", 1.0]
- ["VFWMACC_VV", 1.0]
- ["VFWMSAC_VF", 1.0]
- ["VFWMSAC_VV", 1.0]
- ["VFWMUL_VF", 1.0]
- ["VFWMUL_VV", 1.0]
- ["VFWNMACC_VF", 1.0]
- ["VFWNMACC_VV", 1.0]
- ["VFWNMSAC_VF", 1.0]
- ["VFWNMSAC_VV", 1.0]
- ["VFWREDOSUM_VS", 1.0]
- ["VFWREDUSUM_VS", 1.0]
- ["VFWSUB_VF", 1.0]
- ["VFWSUB_VV", 1.0]
- ["VFWSUB_WF", 1.0]
- ["VFWSUB_WV", 1.0]
- ["VID_V", 1.0]
- ["VIOTA_M", 1.0]
- ["VL1RE16_V", 1.0]
- ["VL1RE32_V", 1.0]
- ["VL1RE64_V", 1.0]
- ["VL1RE8_V", 1.0]
- ["VL2RE16_V", 1.0]
- ["VL2RE32_V", 1.0]
- ["VL2RE64_V", 1.0]
- ["VL2RE8_V", 1.0]
- ["VL4RE16_V", 1.0]
- ["VL4RE32_V", 1.0]
- ["VL4RE64_V", 1.0]
- ["VL4RE8_V", 1.0]
- ["VL8RE16_V", 1.0]
- ["VL8RE32_V", 1.0]
- ["VL8RE64_V", 1.0]
- ["VL8RE8_V", 1.0]
- ["VLE16FF_V", 1.0]
- ["VLE16_V", 1.0]
- ["VLE32FF_V", 1.0]
- ["VLE32_V", 1.0]
- ["VLE64FF_V", 1.0]
- ["VLE64_V", 1.0]
- ["VLE8FF_V", 1.0]
- ["VLE8_V", 1.0]
- ["VLM_V", 1.0]
- ["VLOXEI16_V", 1.0]
- ["VLOXEI32_V", 1.0]
- ["VLOXEI64_V", 1.0]
- ["VLOXEI8_V", 1.0]
- ["VLOXSEG2EI16_V", 1.0]
- ["VLOXSEG2EI32_V", 1.0]
- ["VLOXSEG2EI64_V", 1.0]
- ["VLOXSEG2EI8_V", 1.0]
- ["VLOXSEG3EI16_V", 1.0]
- ["VLOXSEG3EI32_V", 1.0]
- ["VLOXSEG3EI64_V", 1.0]
- ["VLOXSEG3EI8_V", 1.0]
- ["VLOXSEG4EI16_V", 1.0]
- ["VLOXSEG4EI32_V", 1.0]
- ["VLOXSEG4EI64_V", 1.0]
- ["VLOXSEG4EI8_V", 1.0]
- ["VLOXSEG5EI16_V", 1.0]
- ["VLOXSEG5EI32_V", 1.0]
- ["VLOXSEG5EI64_V", 1.0]
- ["VLOXSEG5EI8_V", 1.0]
- ["VLOXSEG6EI16_V", 1.0]
- ["VLOXSEG6EI32_V", 1.0]
- ["VLOXSEG6EI64_V", 1.0]
- ["VLOXSEG6EI8_V", 1.0]
- ["VLOXSEG7EI16_V", 1.0]
- ["VLOXSEG7EI32_V", 1.0]
- ["VLOXSEG7EI64_V", 1.0]
- ["VLOXSEG7EI8_V", 1.0]
- ["VLOXSEG8EI16_V", 1.0]
- ["VLOXSEG8EI32_V", 1.0]
- ["VLOXSEG8EI64_V", 1.0]
- ["VLOXSEG8EI8_V", 1.0]
- ["VLSE16_V", 1.0]
- ["VLSE32_V", 1.0]
- ["VLSE64_V", 1.0]
- ["VLSE8_V", 1.0]
- ["VLSEG2E16FF_V", 1.0]
- ["VLSEG2E16_V", 1.0]
- ["VLSEG2E32FF_V", 1.0]
- ["VLSEG2E32_V", 1.0]
- ["VLSEG2E64FF_V", 1.0]
- ["VLSEG2E64_V", 1.0]
- ["VLSEG2E8FF_V", 1.0]
- ["VLSEG2E8_V", 1.0]
- ["VLSEG3E16FF_V", 1.0]
- ["VLSEG3E16_V", 1.0]
- ["VLSEG3E32FF_V", 1.0]
- ["VLSEG3E32_V", 1.0]
- ["VLSEG3E64FF_V", 1.0]
- ["VLSEG3E64_V", 1.0]
- ["VLSEG3E8FF_V", 1.0]
- ["VLSEG3E8_V", 1.0]
- ["VLSEG4E16FF_V", 1.0]
- ["VLSEG4E16_V", 1.0]
- ["VLSEG4E32FF_V", 1.0]
- ["VLSEG4E32_V", 1.0]
- ["VLSEG4E64FF_V", 1.0]
- ["VLSEG4E64_V", 1.0]
- ["VLSEG4E8FF_V", 1.0]
- ["VLSEG4E8_V", 1.0]
- ["VLSEG5E16FF_V", 1.0]
- ["VLSEG5E16_V", 1.0]
- ["VLSEG5E32FF_V", 1.0]
- ["VLSEG5E32_V", 1.0]
- ["VLSEG5E64FF_V", 1.0]
- ["VLSEG5E64_V", 1.0]
- ["VLSEG5E8FF_V", 1.0]
- ["VLSEG5E8_V", 1.0]
- ["VLSEG6E16FF_V", 1.0]
- ["VLSEG6E16_V", 1.0]
- ["VLSEG6E32FF_V", 1.0]
- ["VLSEG6E32_V", 1.0]
- ["VLSEG6E64FF_V", 1.0]
- ["VLSEG6E64_V", 1.0]
- ["VLSEG6E8FF_V", 1.0]
- ["VLSEG6E8_V", 1.0]
- ["VLSEG7E16FF_V", 1.0]
- ["VLSEG7E16_V", 1.0]
- ["VLSEG7E32FF_V", 1.0]
- ["VLSEG7E32_V", 1.0]
- ["VLSEG7E64FF_V", 1.0]
- ["VLSEG7E64_V", 1.0]
- ["VLSEG7E8FF_V", 1.0]
- ["VLSEG7E8_V", 1.0]
- ["VLSEG8E16FF_V", 1.0]
- ["VLSEG8E16_V", 1.0]
- ["VLSEG8E32FF_V", 1.0]
- ["VLSEG8E32_V", 1.0]
- ["VLSEG8E64FF_V", 1.0]
- ["VLSEG8E64_V", 1.0]
- ["VLSEG8E8FF_V", 1.0]
- ["VLSEG8E8_V", 1.0]
- ["VLSSEG2E16_V", 1.0]
- ["VLSSEG2E32_V", 1.0]
- ["VLSSEG2E64_V", 1.0]
- ["VLSSEG2E8_V", 1.0]
- ["VLSSEG3E16_V", 1.0]
- ["VLSSEG3E32_V", 1.0]
- ["VLSSEG3E64_V", 1.0]
- ["VLSSEG3E8_V", 1.0]
- ["VLSSEG4E16_V", 1.0]
- ["VLSSEG4E32_V", 1.0]
- ["VLSSEG4E64_V", 1.0]
- ["VLSSEG4E8_V", 1.0]
- ["VLSSEG5E16_V", 1.0]
- ["VLSSEG5E32_V", 1.0]
- ["VLSSEG5E64_V", 1.0]
- ["VLSSEG5E8_V", 1.0]
- ["VLSSEG6E16_V", 1.0]
- ["VLSSEG6E32_V", 1.0]
- ["VLSSEG6E64_V", 1.0]
- ["VLSSEG6E8_V", 1.0]
- ["VLSSEG7E16_V", 1.0]
- ["VLSSEG7E32_V", 1.0]
- ["VLSSEG7E64_V", 1.0]
- ["VLSSEG7E8_V", 1.0]
- ["VLSSEG8E16_V", 1.0]
- ["VLSSEG8E32_V", 1.0]
- ["VLSSEG8E64_V", 1.0]
- ["VLSSEG8E8_V", 1.0]
- ["VLUXEI16_V", 1.0]
- ["VLUXEI32_V", 1.0]
- ["VLUXEI64_V", 1.0]
- ["VLUXEI8_V", 1.0]
- ["VLUXSEG2EI16_V", 1.0]
- ["VLUXSEG2EI32_V", 1.0]
- ["VLUXSEG2EI64_V", 1.0]
- ["VLUXSEG2EI8_V", 1.0]
- ["VLUXSEG3EI16_V", 1.0]
- ["VLUXSEG3EI32_V", 1.0]
- ["VLUXSEG3EI64_V", 1.0]
- ["VLUXSEG3EI8_V", 1.0]
- ["VLUXSEG4EI16_V", 1.0]
- ["VLUXSEG4EI32_V", 1.0]
- ["VLUXSEG4EI64_V", 1.0]
- ["VLUXSEG4EI8_V", 1.0]
- ["VLUXSEG5EI16_V", 1.0]
- ["VLUXSEG5EI32_V", 1.0]
- ["VLUXSEG5EI64_V", 1.0]
- ["VLUXSEG5EI8_V", 1.0]
- ["VLUXSEG6EI16_V", 1.0]
- ["VLUXSEG6EI32_V", 1.0]
- ["VLUXSEG6EI64_V", 1.0]
- ["VLUXSEG6EI8_V", 1.0]
- ["VLUXSEG7EI16_V", 1.0]
- ["VLUXSEG7EI32_V", 1.0]
- ["VLUXSEG7EI64_V", 1.0]
- ["VLUXSEG7EI8_V", 1.0]
- ["VLUXSEG8EI16_V", 1.0]
- ["VLUXSEG8EI32_V", 1.0]
- ["VLUXSEG8EI64_V", 1.0]
- ["VLUXSEG8EI8_V", 1.0]
- ["VMACC_VV", 1.0]
- ["VMACC_VX", 1.0]
- ["VMADC_VI", 1.0]
- ["VMADC_VIM", 1.0]
- ["VMADC_VV", 1.0]
- ["VMADC_VVM", 1.0]
- ["VMADC_VX", 1.0]
- ["VMADC_VXM", 1.0]
- ["VMADD_VV", 1.0]
- ["VMADD_VX", 1.0]
- ["VMANDN_MM", 1.0]
- ["VMAND_MM", 1.0]
- ["VMAXU_VV", 1.0]
- ["VMAXU_VX", 1.0]
- ["VMAX_VV", 1.0]
- ["VMAX_VX", 1.0]
- ["VMERGE_VIM", 1.0]
- ["VMERGE_VVM", 1.0]
- ["VMERGE_VXM", 1.0]
- ["VMFEQ_VF", 1.0]
- ["VMFEQ_VV", 1.0]
- ["VMFGE_VF", 1.0]
- ["VMFGT_VF", 1.0]
- ["VMFLE_VF", 1.0]
- ["VMFLE_VV", 1.0]
- ["VMFLT_VF", 1.0]
- ["VMFLT_VV", 1.0]
- ["VMFNE_VF", 1.0]
- ["VMFNE_VV", 1.0]
- ["VMINU_VV", 1.0]
- ["VMINU_VX", 1.0]
- ["VMIN_VV", 1.0]
- ["VMIN_VX", 1.0]
- ["VMNAND_MM", 1.0]
- ["VMNOR_MM", 1.0]
- ["VMORN_MM", 1.0]
- ["VMOR_MM", 1.0]
- ["VMSBC_VV", 1.0]
- ["VMSBC_VVM", 1.0]
- ["VMSBC_VX", 1.0]
- ["VMSBC_VXM", 1.0]
- ["VMSBF_M", 1.0]
- ["VMSEQ_VI", 1.0]
- ["VMSEQ_VV", 1.0]
- ["VMSEQ_VX", 1.0]
- ["VMSGTU_VI", 1.0]
- ["VMSGTU_VX", 1.0]
- ["VMSGT_VI", 1.0]
- ["VMSGT_VX", 1.0]
- ["VMSIF_M", 1.0]
- ["VMSLEU_VI", 1.0]
- ["VMSLEU_VV", 1.0]
- ["VMSLEU_VX", 1.0]
- ["VMSLE_VI", 1.0]
- ["VMSLE_VV", 1.0]
- ["VMSLE_VX", 1.0]
- ["VMSLTU_VV", 1.0]
- ["VMSLTU_VX", 1.0]
- ["VMSLT_VV", 1.0]
- ["VMSLT_VX", 1.0]
- ["VMSNE_VI", 1.0]
- ["VMSNE_VV", 1.0]
- ["VMSNE_VX", 1.0]
- ["VMSOF_M", 1.0]
- ["VMULHSU_VV", 1.0]
- ["VMULHSU_VX", 1.0]
- ["VMULHU_VV", 1.0]
- ["VMULHU_VX", 1.0]
- ["VMULH_VV", 1.0]
- ["VMULH_VX", 1.0]
- ["VMUL_VV", 1.0]
- ["VMUL_VX", 1.0]
- ["VMV1R_V", 1.0]
- ["VMV2R_V", 1.0]
- ["VMV4R_V", 1.0]
- ["VMV8R_V", 1.0]
- ["VMV_S_X", 1.0]
- ["VMV_V_I", 1.0]
- ["VMV_V_V", 1.0]
- ["VMV_V_X", 1.0]
- ["VMV_X_S", 1.0]
- ["VMXNOR_MM", 1.0]
- ["VMXOR_MM", 1.0]
- ["VNCLIPU_WI", 1.0]
- ["VNCLIPU_WV", 1.0]
- ["VNCLIPU_WX", 1.0]
- ["VNCLIP_WI", 1.0]
- ["VNCLIP_WV", 1.0]
- ["VNCLIP_WX", 1.0]
- ["VNMSAC_VV", 1.0]
- ["VNMSAC_VX", 1.0]
- ["VNMSUB_VV", 1.0]
- ["VNMSUB_VX", 1.0]
- ["VNSRA_WI", 1.0]
- ["VNSRA_WV", 1.0]
- ["VNSRA_WX", 1.0]
- ["VNSRL_WI", 1.0]
- ["VNSRL_WV", 1.0]
- ["VNSRL_WX", 1.0]
- ["VOR_VI", 1.0]
- ["VOR_VV", 1.0]
- ["VOR_VX", 1.0]
- ["VREDAND_VS", 1.0]
- ["VREDMAXU_VS", 1.0]
- ["VREDMAX_VS", 1.0]
- ["VREDMINU_VS", 1.0]
- ["VREDMIN_VS", 1.0]
- ["VREDOR_VS", 1.0]
- ["VREDSUM_VS", 1.0]
- ["VREDXOR_VS", 1.0]
- ["VREMU_VV", 1.0]
- ["VREMU_VX", 1.0]
- ["VREM_VV", 1.0]
- ["VREM_VX", 1.0]
- ["VRGATHEREI16_VV", 1.0]
- ["VRGATHER_VI", 1.0]
- ["VRGATHER_VV", 1.0]
- ["VRGATHER_VX", 1.0]
- ["VRSUB_VI", 1.0]
- ["VRSUB_VX", 1.0]
- ["VS1R_V", 1.0]
- ["VS2R_V", 1.0]
- ["VS4R_V", 1.0]
- ["VS8R_V", 1.0]
- ["VSADDU_VI", 1.0]
- ["VSADDU_VV", 1.0]
- ["VSADDU_VX", 1.0]
- ["VSADD_VI", 1.0]
- ["VSADD_VV", 1.0]
- ["VSADD_VX", 1.0]
- ["VSBC_VVM", 1.0]
- ["VSBC_VXM", 1.0]
- ["VSE16_V", 1.0]
- ["VSE32_V", 1.0]
- ["VSE64_V", 1.0]
- ["VSE8_V", 1.0]
- ["VSEXT_VF2", 1.0]
- ["VSEXT_VF4", 1.0]
- ["VSEXT_VF8", 1.0]
- ["VSLIDE1DOWN_VX", 1.0]
- ["VSLIDE1UP_VX", 1.0]
- ["VSLIDEDOWN_VI", 1.0]
- ["VSLIDEDOWN_VX", 1.0]
- ["VSLIDEUP_VI", 1.0]
- ["VSLIDEUP_VX", 1.0]
- ["VSLL_VI", 1.0]
- ["VSLL_VV", 1.0]
- ["VSLL_VX", 1.0]
- ["VSMUL_VV", 1.0]
- ["VSMUL_VX", 1.0]
- ["VSM_V", 1.0]
- ["VSOXEI16_V", 1.0]
- ["VSOXEI32_V", 1.0]
- ["VSOXEI64_V", 1.0]
- ["VSOXEI8_V", 1.0]
- ["VSOXSEG2EI16_V", 1.0]
- ["VSOXSEG2EI32_V", 1.0]
- ["VSOXSEG2EI64_V", 1.0]
- ["VSOXSEG2EI8_V", 1.0]
- ["VSOXSEG3EI16_V", 1.0]
- ["VSOXSEG3EI32_V", 1.0]
- ["VSOXSEG3EI64_V", 1.0]
- ["VSOXSEG3EI8_V", 1.0]
- ["VSOXSEG4EI16_V", 1.0]
- ["VSOXSEG4EI32_V", 1.0]
- ["VSOXSEG4EI64_V", 1.0]
- ["VSOXSEG4EI8_V", 1.0]
- ["VSOXSEG5EI16_V", 1.0]
- ["VSOXSEG5EI32_V", 1.0]
- ["VSOXSEG5EI64_V", 1.0]
- ["VSOXSEG5EI8_V", 1.0]
- ["VSOXSEG6EI16_V", 1.0]
- ["VSOXSEG6EI32_V", 1.0]
- ["VSOXSEG6EI64_V", 1.0]
- ["VSOXSEG6EI8_V", 1.0]
- ["VSOXSEG7EI16_V", 1.0]
- ["VSOXSEG7EI32_V", 1.0]
- ["VSOXSEG7EI64_V", 1.0]
- ["VSOXSEG7EI8_V", 1.0]
- ["VSOXSEG8EI16_V", 1.0]
- ["VSOXSEG8EI32_V", 1.0]
- ["VSOXSEG8EI64_V", 1.0]
- ["VSOXSEG8EI8_V", 1.0]
- ["VSRA_VI", 1.0]
- ["VSRA_VV", 1.0]
- ["VSRA_VX", 1.0]
- ["VSRL_VI", 1.0]
- ["VSRL_VV", 1.0]
- ["VSRL_VX", 1.0]
- ["VSSE16_V", 1.0]
- ["VSSE32_V", 1.0]
- ["VSSE64_V", 1.0]
- ["VSSE8_V", 1.0]
- ["VSSEG2E16_V", 1.0]
- ["VSSEG2E32_V", 1.0]
- ["VSSEG2E64_V", 1.0]
- ["VSSEG2E8_V", 1.0]
- ["VSSEG3E16_V", 1.0]
- ["VSSEG3E32_V", 1.0]
- ["VSSEG3E64_V", 1.0]
- ["VSSEG3E8_V", 1.0]
- ["VSSEG4E16_V", 1.0]
- ["VSSEG4E32_V", 1.0]
- ["VSSEG4E64_V", 1.0]
- ["VSSEG4E8_V", 1.0]
- ["VSSEG5E16_V", 1.0]
- ["VSSEG5E32_V", 1.0]
- ["VSSEG5E64_V", 1.0]
- ["VSSEG5E8_V", 1.0]
- ["VSSEG6E16_V", 1.0]
- ["VSSEG6E32_V", 1.0]
- ["VSSEG6E64_V", 1.0]
- ["VSSEG6E8_V", 1.0]
- ["VSSEG7E16_V", 1.0]
- ["VSSEG7E32_V", 1.0]
- ["VSSEG7E64_V", 1.0]
- ["VSSEG7E8_V", 1.0]
- ["VSSEG8E16_V", 1.0]
- ["VSSEG8E32_V", 1.0]
- ["VSSEG8E64_V", 1.0]
- ["VSSEG8E8_V", 1.0]
- ["VSSRA_VI", 1.0]
- ["VSSRA_VV", 1.0]
- ["VSSRA_VX", 1.0]
- ["VSSRL_VI", 1.0]
- ["VSSRL_VV", 1.0]
- ["VSSRL_VX", 1.0]
- ["VSSSEG2E16_V", 1.0]
- ["VSSSEG2E32_V", 1.0]
- ["VSSSEG2E64_V", 1.0]
- ["VSSSEG2E8_V", 1.0]
- ["VSSSEG3E16_V", 1.0]
- ["VSSSEG3E32_V", 1.0]
- ["VSSSEG3E64_V", 1.0]
- ["VSSSEG3E8_V", 1.0]
- ["VSSSEG4E16_V", 1.0]
- ["VSSSEG4E32_V", 1.0]
- ["VSSSEG4E64_V", 1.0]
- ["VSSSEG4E8_V", 1.0]
- ["VSSSEG5E16_V", 1.0]
- ["VSSSEG5E32_V", 1.0]
- ["VSSSEG5E64_V", 1.0]
- ["VSSSEG5E8_V", 1.0]
- ["VSSSEG6E16_V", 1.0]
- ["VSSSEG6E32_V", 1.0]
- ["VSSSEG6E64_V", 1.0]
- ["VSSSEG6E8_V", 1.0]
- ["VSSSEG7E16_V", 1.0]
- ["VSSSEG7E32_V", 1.0]
- ["VSSSEG7E64_V", 1.0]
- ["VSSSEG7E8_V", 1.0]
- ["VSSSEG8E16_V", 1.0]
- ["VSSSEG8E32_V", 1.0]
- ["VSSSEG8E64_V", 1.0]
- ["VSSSEG8E8_V", 1.0]
- ["VSSUBU_VV", 1.0]
- ["VSSUBU_VX", 1.0]
- ["VSSUB_VV", 1.0]
- ["VSSUB_VX", 1.0]
- ["VSUB_VV", 1.0]
- ["VSUB_VX", 1.0]
- ["VSUXEI16_V", 1.0]
- ["VSUXEI32_V", 1.0]
- ["VSUXEI64_V", 1.0]
- ["VSUXEI8_V", 1.0]
- ["VSUXSEG2EI16_V", 1.0]
- ["VSUXSEG2EI32_V", 1.0]
- ["VSUXSEG2EI64_V", 1.0]
- ["VSUXSEG2EI8_V", 1.0]
- ["VSUXSEG3EI16_V", 1.0]
- ["VSUXSEG3EI32_V", 1.0]
- ["VSUXSEG3EI64_V", 1.0]
- ["VSUXSEG3EI8_V", 1.0]
- ["VSUXSEG4EI16_V", 1.0]
- ["VSUXSEG4EI32_V", 1.0]
- ["VSUXSEG4EI64_V", 1.0]
- ["VSUXSEG4EI8_V", 1.0]
- ["VSUXSEG5EI16_V", 1.0]
- ["VSUXSEG5EI32_V", 1.0]
- ["VSUXSEG5EI64_V", 1.0]
- ["VSUXSEG5EI8_V", 1.0]
- ["VSUXSEG6EI16_V", 1.0]
- ["VSUXSEG6EI32_V", 1.0]
- ["VSUXSEG6EI64_V", 1.0]
- ["VSUXSEG6EI8_V", 1.0]
- ["VSUXSEG7EI16_V", 1.0]
- ["VSUXSEG7EI32_V", 1.0]
- ["VSUXSEG7EI64_V", 1.0]
- ["VSUXSEG7EI8_V", 1.0]
- ["VSUXSEG8EI16_V", 1.0]
- ["VSUXSEG8EI32_V", 1.0]
- ["VSUXSEG8EI64_V", 1.0]
- ["VSUXSEG8EI8_V", 1.0]
- ["VWADDU_VV", 1.0]
- ["VWADDU_VX", 1.0]
- ["VWADDU_WV", 1.0]
- ["VWADDU_WX", 1.0]
- ["VWADD_VV", 1.0]
- ["VWADD_VX", 1.0]
- ["VWADD_WV", 1.0]
- ["VWADD_WX", 1.0]
- ["VWMACCSU_VV", 1.0]
- ["VWMACCSU_VX", 1.0]
- ["VWMACCUS_VX", 1.0]
- ["VWMACCU_VV", 1.0]
- ["VWMACCU_VX", 1.0]
- ["VWMACC_VV", 1.0]
- ["VWMACC_VX", 1.0]
- ["VWMULSU_VV", 1.0]
- ["VWMULSU_VX", 1.0]
- ["VWMULU_VV", 1.0]
- ["VWMULU_VX", 1.0]
- ["VWMUL_VV", 1.0]
- ["VWMUL_VX", 1.0]
- ["VWREDSUMU_VS", 1.0]
- ["VWREDSUM_VS", 1.0]
- ["VWSUBU_VV", 1.0]
- ["VWSUBU_VX", 1.0]
- ["VWSUBU_WV", 1.0]
- ["VWSUBU_WX", 1.0]
- ["VWSUB_VV", 1.0]
- ["VWSUB_VX", 1.0]
- ["VWSUB_WV", 1.0]
- ["VWSUB_WX", 1.0]
- ["VXOR_VI", 1.0]
- ["VXOR_VV", 1.0]
- ["VXOR_VX", 1.0]
- ["VZEXT_VF2", 1.0]
- ["VZEXT_VF4", 1.0]
- ["VZEXT_VF8", 1.0]

12
ci-tests/test-spike
View File

@ -20,7 +20,7 @@ make install
# build tests
rm -rf $RUN
mkdir $RUN
mkdir -p $RUN
cd $RUN
riscv64-linux-gnu-gcc -static -O2 -o hello $CI/hello.c
riscv64-linux-gnu-gcc -static -O2 -o dummy-slliuw $CI/dummy-slliuw.c
@ -28,12 +28,12 @@ riscv64-linux-gnu-gcc -static -O2 -o customcsr $CI/customcsr.c
riscv64-linux-gnu-gcc -static -O2 -o atomics $CI/atomics.c
# run snippy-based tests
wget https://github.com/syntacore/snippy/releases/download/snippy-2.0/snippy-2.0.tar.gz
tar xzf "snippy-2.0.tar.gz"
wget https://github.com/syntacore/snippy/releases/download/snippy-2.1/snippy-x86_64-linux.tar.xz
tar xf snippy-x86_64-linux.tar.xz
# test that snippy runs
./llvm-snippy --version | grep "Snippy version"
"$ROOT"/ci-tests/generate-snippy-tests.sh "$RUN" "$ROOT"/ci-tests/snippy-tests
"$ROOT"/ci-tests/run-snippy-tests.sh snippy-tests "$INSTALL"/bin/spike
bin/llvm-snippy --version | grep "Snippy version: 2.1.0"
PATH="$PATH:$RUN/bin" "$ROOT"/ci-tests/run-snippy-tests.sh "$RUN" "$ROOT"/ci-tests/snippy-tests "$INSTALL"/bin/spike
# check that including sim.h in an external project works
g++ -std=c++2a -I$INSTALL/include -L$INSTALL/lib $CI/testlib.cc -lriscv -o test-libriscv

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