Andrew Waterman
3 years ago
committed by
GitHub
GitHub
9 changed files with 328 additions and 312 deletions
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// See LICENSE for license details.
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#ifndef _RISCV_DECODE_MACROS_H |
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#define _RISCV_DECODE_MACROS_H |
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#include "config.h" |
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#include "decode.h" |
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#include "encoding.h" |
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#include "common.h" |
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#include "softfloat_types.h" |
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#include "specialize.h" |
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// helpful macros, etc
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#define MMU (*p->get_mmu()) |
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#define STATE (*p->get_state()) |
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#define FLEN (p->get_flen()) |
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#define CHECK_REG(reg) ((void) 0) |
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#define READ_REG(reg) (CHECK_REG(reg), STATE.XPR[reg]) |
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#define READ_FREG(reg) STATE.FPR[reg] |
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#define RD READ_REG(insn.rd()) |
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#define RS1 READ_REG(insn.rs1()) |
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#define RS2 READ_REG(insn.rs2()) |
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#define RS3 READ_REG(insn.rs3()) |
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#define WRITE_RD(value) WRITE_REG(insn.rd(), value) |
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#ifndef RISCV_ENABLE_COMMITLOG |
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# define WRITE_REG(reg, value) ({ CHECK_REG(reg); STATE.XPR.write(reg, value); }) |
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# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) |
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# define WRITE_VSTATUS {} |
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#else |
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/* 0 : int
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* 1 : floating |
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* 2 : vector reg |
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* 3 : vector hint |
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* 4 : csr |
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*/ |
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# define WRITE_REG(reg, value) ({ \ |
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reg_t wdata = (value); /* value may have side effects */ \ |
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STATE.log_reg_write[(reg) << 4] = {wdata, 0}; \ |
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CHECK_REG(reg); \ |
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STATE.XPR.write(reg, wdata); \ |
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}) |
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# define WRITE_FREG(reg, value) ({ \ |
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freg_t wdata = freg(value); /* value may have side effects */ \ |
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STATE.log_reg_write[((reg) << 4) | 1] = wdata; \ |
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DO_WRITE_FREG(reg, wdata); \ |
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}) |
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# define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; |
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#endif |
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// RVC macros
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#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) |
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#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) |
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#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) |
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#define RVC_RS1 READ_REG(insn.rvc_rs1()) |
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#define RVC_RS2 READ_REG(insn.rvc_rs2()) |
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#define RVC_RS1S READ_REG(insn.rvc_rs1s()) |
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#define RVC_RS2S READ_REG(insn.rvc_rs2s()) |
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#define RVC_FRS2 READ_FREG(insn.rvc_rs2()) |
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#define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) |
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#define RVC_SP READ_REG(X_SP) |
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// Zc* macros
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#define RVC_SREG1 (Sn(insn.rvc_sreg1())) |
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#define RVC_SREG2 (Sn(insn.rvc_sreg2())) |
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#define SP READ_REG(X_SP) |
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#define RA READ_REG(X_RA) |
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// FPU macros
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#define READ_ZDINX_REG(reg) (xlen == 32 ? f64(READ_REG_PAIR(reg)) : f64(STATE.XPR[reg] & (uint64_t)-1)) |
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#define READ_FREG_H(reg) (p->extension_enabled(EXT_ZFINX) ? f16(STATE.XPR[reg] & (uint16_t)-1) : f16(READ_FREG(reg))) |
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#define READ_FREG_F(reg) (p->extension_enabled(EXT_ZFINX) ? f32(STATE.XPR[reg] & (uint32_t)-1) : f32(READ_FREG(reg))) |
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#define READ_FREG_D(reg) (p->extension_enabled(EXT_ZFINX) ? READ_ZDINX_REG(reg) : f64(READ_FREG(reg))) |
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#define FRS1 READ_FREG(insn.rs1()) |
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#define FRS2 READ_FREG(insn.rs2()) |
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#define FRS3 READ_FREG(insn.rs3()) |
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#define FRS1_H READ_FREG_H(insn.rs1()) |
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#define FRS1_F READ_FREG_F(insn.rs1()) |
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#define FRS1_D READ_FREG_D(insn.rs1()) |
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#define FRS2_H READ_FREG_H(insn.rs2()) |
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#define FRS2_F READ_FREG_F(insn.rs2()) |
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#define FRS2_D READ_FREG_D(insn.rs2()) |
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#define FRS3_H READ_FREG_H(insn.rs3()) |
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#define FRS3_F READ_FREG_F(insn.rs3()) |
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#define FRS3_D READ_FREG_D(insn.rs3()) |
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#define dirty_fp_state STATE.sstatus->dirty(SSTATUS_FS) |
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#define dirty_ext_state STATE.sstatus->dirty(SSTATUS_XS) |
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#define dirty_vs_state STATE.sstatus->dirty(SSTATUS_VS) |
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#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) |
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#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) |
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#define WRITE_FRD_H(value) \ |
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do { \ |
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if (p->extension_enabled(EXT_ZFINX)) \ |
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WRITE_REG(insn.rd(), sext_xlen((int16_t)((value).v))); \ |
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else { \ |
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WRITE_FRD(value); \ |
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} \ |
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} while (0) |
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#define WRITE_FRD_F(value) \ |
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do { \ |
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if (p->extension_enabled(EXT_ZFINX)) \ |
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WRITE_REG(insn.rd(), sext_xlen((value).v)); \ |
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else { \ |
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WRITE_FRD(value); \ |
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} \ |
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} while (0) |
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#define WRITE_FRD_D(value) \ |
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do { \ |
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if (p->extension_enabled(EXT_ZFINX)) { \ |
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if (xlen == 32) { \ |
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uint64_t val = (value).v; \ |
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WRITE_RD_PAIR(val); \ |
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} else { \ |
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WRITE_REG(insn.rd(), (value).v); \ |
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} \ |
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} else { \ |
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WRITE_FRD(value); \ |
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} \ |
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} while (0) |
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#define SHAMT (insn.i_imm() & 0x3F) |
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#define BRANCH_TARGET (pc + insn.sb_imm()) |
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#define JUMP_TARGET (pc + insn.uj_imm()) |
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#define RM ({ int rm = insn.rm(); \ |
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if (rm == 7) rm = STATE.frm->read(); \ |
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if (rm > 4) throw trap_illegal_instruction(insn.bits()); \ |
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rm; }) |
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#define require_privilege(p) require(STATE.prv >= (p)) |
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#define require_novirt() (unlikely(STATE.v) ? throw trap_virtual_instruction(insn.bits()) : (void) 0) |
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#define require_hs_qualified(cond) (STATE.v && !(cond) ? require_novirt() : require(cond)) |
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#define require_privilege_hs_qualified(p) require_hs_qualified(STATE.prv >= (p)) |
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#define require_rv64 require(xlen == 64) |
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#define require_rv32 require(xlen == 32) |
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#define require_extension(s) require(p->extension_enabled(s)) |
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#define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B)); |
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#define require_impl(s) require(p->supports_impl(s)) |
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#define require_fs require(STATE.sstatus->enabled(SSTATUS_FS)) |
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#define require_fp STATE.fflags->verify_permissions(insn, false) |
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#define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS)) |
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#define require_vector_vs require(STATE.sstatus->enabled(SSTATUS_VS)) |
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#define require_vector(alu) \ |
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do { \ |
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require_vector_vs; \ |
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require_extension('V'); \ |
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require(!P.VU.vill); \ |
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if (alu && !P.VU.vstart_alu) \ |
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require(P.VU.vstart->read() == 0); \ |
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WRITE_VSTATUS; \ |
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dirty_vs_state; \ |
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} while (0); |
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#define require_vector_novtype(is_log) \ |
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do { \ |
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require_vector_vs; \ |
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require_extension('V'); \ |
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if (is_log) \ |
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WRITE_VSTATUS; \ |
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dirty_vs_state; \ |
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} while (0); |
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#define require_align(val, pos) require(is_aligned(val, pos)) |
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#define require_noover(astart, asize, bstart, bsize) \ |
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require(!is_overlapped(astart, asize, bstart, bsize)) |
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#define require_noover_widen(astart, asize, bstart, bsize) \ |
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require(!is_overlapped_widen(astart, asize, bstart, bsize)) |
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#define require_vm do { if (insn.v_vm() == 0) require(insn.rd() != 0); } while (0); |
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#define require_envcfg(field) \ |
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do { \ |
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if (((STATE.prv != PRV_M) && (m##field == 0)) || \ |
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((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \ |
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throw trap_illegal_instruction(insn.bits()); \ |
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else if (STATE.v && ((h##field == 0) || \ |
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((STATE.prv == PRV_U) && (s##field == 0)))) \ |
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throw trap_virtual_instruction(insn.bits()); \ |
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} while (0); |
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#define require_zcmp_pushpop \ |
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do { \ |
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require_extension(EXT_ZCMP); \ |
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reg_t rlist = insn.rvc_rlist(); \ |
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require(rlist >= 4); \ |
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\ |
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if (p->extension_enabled('E')) { \ |
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require(rlist <= 6); \ |
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} \ |
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} while (0); |
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#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ |
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STATE.fflags->write(STATE.fflags->read() | softfloat_exceptionFlags); \ |
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} \ |
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softfloat_exceptionFlags = 0; }) |
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#define sext32(x) ((sreg_t)(int32_t)(x)) |
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#define zext32(x) ((reg_t)(uint32_t)(x)) |
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#define sext_xlen(x) (((sreg_t)(x) << (64 - xlen)) >> (64 - xlen)) |
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#define zext(x, pos) (((reg_t)(x) << (64 - (pos))) >> (64 - (pos))) |
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#define zext_xlen(x) zext(x, xlen) |
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#define set_pc(x) \ |
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do { p->check_pc_alignment(x); \ |
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npc = sext_xlen(x); \ |
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} while (0) |
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#define set_pc_and_serialize(x) \ |
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do { reg_t __npc = (x) & p->pc_alignment_mask(); \ |
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npc = PC_SERIALIZE_AFTER; \ |
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STATE.pc = __npc; \ |
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} while (0) |
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class wait_for_interrupt_t {}; |
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#define wfi() \ |
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do { set_pc_and_serialize(npc); \ |
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throw wait_for_interrupt_t(); \ |
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} while (0) |
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#define serialize() set_pc_and_serialize(npc) |
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/* Sentinel PC values to serialize simulator pipeline */ |
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#define PC_SERIALIZE_BEFORE 3 |
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#define PC_SERIALIZE_AFTER 5 |
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#define invalid_pc(pc) ((pc) & 1) |
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/* Convenience wrappers to simplify softfloat code sequences */ |
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#define isBoxedF16(r) (isBoxedF32(r) && ((uint64_t)((r.v[0] >> 16) + 1) == ((uint64_t)1 << 48))) |
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#define unboxF16(r) (isBoxedF16(r) ? (uint16_t)r.v[0] : defaultNaNF16UI) |
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#define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) |
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#define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) |
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#define isBoxedF64(r) ((r.v[1] + 1) == 0) |
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#define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI) |
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inline float16_t f16(uint16_t v) { return { v }; } |
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inline float32_t f32(uint32_t v) { return { v }; } |
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inline float64_t f64(uint64_t v) { return { v }; } |
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inline float16_t f16(freg_t r) { return f16(unboxF16(r)); } |
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inline float32_t f32(freg_t r) { return f32(unboxF32(r)); } |
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inline float64_t f64(freg_t r) { return f64(unboxF64(r)); } |
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inline float128_t f128(freg_t r) { return r; } |
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inline freg_t freg(float16_t f) { return { ((uint64_t)-1 << 16) | f.v, (uint64_t)-1 }; } |
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inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; } |
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inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; } |
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inline freg_t freg(float128_t f) { return f; } |
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#define F16_SIGN ((uint16_t)1 << 15) |
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#define F32_SIGN ((uint32_t)1 << 31) |
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#define F64_SIGN ((uint64_t)1 << 63) |
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#define fsgnj16(a, b, n, x) \ |
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f16((f16(a).v & ~F16_SIGN) | ((((x) ? f16(a).v : (n) ? F16_SIGN : 0) ^ f16(b).v) & F16_SIGN)) |
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#define fsgnj32(a, b, n, x) \ |
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f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) |
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#define fsgnj64(a, b, n, x) \ |
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f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) |
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#define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0]) |
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inline float128_t defaultNaNF128() |
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{ |
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float128_t nan; |
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nan.v[1] = defaultNaNF128UI64; |
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nan.v[0] = defaultNaNF128UI0; |
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return nan; |
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} |
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inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x) |
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{ |
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a.v[1] = (a.v[1] & ~F64_SIGN) | (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN); |
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return a; |
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} |
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inline freg_t f128_negate(freg_t a) |
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{ |
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a.v[1] ^= F64_SIGN; |
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return a; |
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} |
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#define validate_csr(which, write) ({ \ |
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if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ |
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STATE.serialized = false; \ |
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/* permissions check occurs in get_csr */ \ |
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(which); }) |
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/* For debug only. This will fail if the native machine's float types are not IEEE */ |
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inline float to_f(float32_t f) { float r; memcpy(&r, &f, sizeof(r)); return r; } |
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inline double to_f(float64_t f) { double r; memcpy(&r, &f, sizeof(r)); return r; } |
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inline long double to_f(float128_t f) { long double r; memcpy(&r, &f, sizeof(r)); return r; } |
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// Vector macros
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#define e8 8 // 8b elements
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#define e16 16 // 16b elements
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#define e32 32 // 32b elements
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#define e64 64 // 64b elements
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#define e128 128 // 128b elements
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#define e256 256 // 256b elements
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#define e512 512 // 512b elements
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#define e1024 1024 // 1024b elements
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#define vsext(x, sew) (((sreg_t)(x) << (64 - sew)) >> (64 - sew)) |
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#define vzext(x, sew) (((reg_t)(x) << (64 - sew)) >> (64 - sew)) |
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#define DEBUG_RVV 0 |
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#if DEBUG_RVV |
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#define DEBUG_RVV_FP_VV \ |
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printf("vfp(%lu) vd=%f vs1=%f vs2=%f\n", i, to_f(vd), to_f(vs1), to_f(vs2)); |
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#define DEBUG_RVV_FP_VF \ |
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printf("vfp(%lu) vd=%f vs1=%f vs2=%f\n", i, to_f(vd), to_f(rs1), to_f(vs2)); |
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#define DEBUG_RVV_FMA_VV \ |
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printf("vfma(%lu) vd=%f vs1=%f vs2=%f vd_old=%f\n", i, to_f(vd), to_f(vs1), to_f(vs2), to_f(vd_old)); |
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#define DEBUG_RVV_FMA_VF \ |
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printf("vfma(%lu) vd=%f vs1=%f vs2=%f vd_old=%f\n", i, to_f(vd), to_f(rs1), to_f(vs2), to_f(vd_old)); |
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#else |
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#define DEBUG_RVV_FP_VV 0 |
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#define DEBUG_RVV_FP_VF 0 |
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#define DEBUG_RVV_FMA_VV 0 |
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#define DEBUG_RVV_FMA_VF 0 |
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#endif |
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#define DECLARE_XENVCFG_VARS(field) \ |
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reg_t m##field = get_field(STATE.menvcfg->read(), MENVCFG_##field); \ |
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reg_t s##field = get_field(STATE.senvcfg->read(), SENVCFG_##field); \ |
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reg_t h##field = get_field(STATE.henvcfg->read(), HENVCFG_##field) |
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#endif |
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