rvv: commitlog: add peek parameter to get_csr

commitlog needs to read all affected csrs but some of them may violate the
permisson.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/processor.cc

@@ -1299,7 +1299,7 @@ void processor_t::set_csr(int which, reg_t val)
 // Note that get_csr is sometimes called when read side-effects should not
 // be actioned.  In other words, Spike cannot currently support CSRs with
 // side effects on reads.
-reg_t processor_t::get_csr(int which, insn_t insn, bool write)
+reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
 {
   uint32_t ctr_en = -1;
   if (state.prv < PRV_M)
@@ -1643,6 +1643,10 @@ out:
   // Check permissions.  Raise virtual-instruction exception if V=1,
   // privileges are insufficient, and the CSR belongs to supervisor or
   // hypervisor.  Raise illegal-instruction exception otherwise.
+
+  if (peek)
+    return res;
+
   unsigned csr_priv = get_field(which, 0x300);
   bool csr_read_only = get_field(which, 0xC00) == 3;
   unsigned priv = state.prv == PRV_S && !state.v ? PRV_HS : state.prv;

riscv/processor.h

@@ -272,8 +272,8 @@ public:
   void reset();
   void step(size_t n); // run for n cycles
   void set_csr(int which, reg_t val);
-  reg_t get_csr(int which, insn_t insn, bool write);
-  reg_t get_csr(int which) { return get_csr(which, insn_t(0), false); }
+  reg_t get_csr(int which, insn_t insn, bool write, bool peek = 0);
+  reg_t get_csr(int which) { return get_csr(which, insn_t(0), false, true); }
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
   unsigned get_xlen() { return xlen; }