Support S-mode vectored interrupts

ChangeLog.md

@@ -1,5 +1,6 @@
 Version 1.0.1-dev
 -----------------
+- Support S-mode vectored interrupts (i.e. stvec[0] is now writable).
 - Added `hasel` debug feature.
 - Added `--dm-no-abstract-csr` command-line option.
 - Renamed `--progsize` to `--dm-progsize`.

riscv/processor.cc

@@ -369,7 +369,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
     // handle the trap in S-mode
-    state.pc = state.stvec;
+    reg_t vector = (state.stvec & 1) && interrupt ? 4*bit : 0;
+    state.pc = (state.stvec & ~(reg_t)1) + vector;
     state.scause = t.cause();
     state.sepc = epc;
     state.stval = t.get_tval();
@@ -564,7 +565,7 @@ void processor_t::set_csr(int which, reg_t val)
       break;
     }
     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
-    case CSR_STVEC: state.stvec = val >> 2 << 2; break;
+    case CSR_STVEC: state.stvec = val & ~(reg_t)2; break;
     case CSR_SSCRATCH: state.sscratch = val; break;
     case CSR_SCAUSE: state.scause = val; break;
     case CSR_STVAL: state.stval = val; break;