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riscv-isa-sim
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change hwacha cause to follow risc-v cause

pull/18/head
Yunsup Lee 12 years ago
parent
1fbcb3dfe3
commit
0c1f8bb8b7
1 changed files with 14 additions and 12 deletions
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  1. 26
      hwacha/hwacha_xcpt.h

26
hwacha/hwacha_xcpt.h
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@ -1,17 +1,19 @@
#ifndef _HWACHA_XCPT_H
#define _HWACHA_XCPT_H
#define HWACHA_CAUSE_ILLEGAL_CFG 0 // AUX: 0=illegal nxpr, 1=illegal nfpr
#define HWACHA_CAUSE_ILLEGAL_INSTRUCTION 1 // AUX: instruction
#define HWACHA_CAUSE_PRIVILEGED_INSTRUCTION 2 // AUX: instruction
#define HWACHA_CAUSE_TVEC_ILLEGAL_REGID 3 // AUX: instruction
#define HWACHA_CAUSE_VF_MISALIGNED_FETCH 4 // AUX: pc
#define HWACHA_CAUSE_VF_FAULT_FETCH 5 // AUX: pc
#define HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION 6 // AUX: pc
#define HWACHA_CAUSE_VF_ILLEGAL_REGID 7 // AUX: pc
#define HWACHA_CAUSE_MISALIGNED_LOAD 8 // AUX: badvaddr
#define HWACHA_CAUSE_MISALIGNED_STORE 9 // AUX: badvaddr
#define HWACHA_CAUSE_FAULT_LOAD 10 // AUX: badvaddr
#define HWACHA_CAUSE_FAULT_STORE 11 // AUX: badvaddr
#include "encoding.h"
#define HWACHA_CAUSE_ILLEGAL_CFG CAUSE_ILLEGAL_INSTRUCTION // AUX: 0=illegal nxpr, 1=illegal nfpr
#define HWACHA_CAUSE_ILLEGAL_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
#define HWACHA_CAUSE_PRIVILEGED_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
#define HWACHA_CAUSE_TVEC_ILLEGAL_REGID CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
#define HWACHA_CAUSE_VF_MISALIGNED_FETCH CAUSE_MISALIGNED_FETCH // AUX: pc
#define HWACHA_CAUSE_VF_FAULT_FETCH CAUSE_FAULT_FETCH // AUX: pc
#define HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: pc
#define HWACHA_CAUSE_VF_ILLEGAL_REGID CAUSE_ILLEGAL_INSTRUCTION // AUX: pc
#define HWACHA_CAUSE_MISALIGNED_LOAD CAUSE_MISALIGNED_LOAD // AUX: badvaddr
#define HWACHA_CAUSE_MISALIGNED_STORE CAUSE_MISALIGNED_STORE // AUX: badvaddr
#define HWACHA_CAUSE_FAULT_LOAD CAUSE_FAULT_LOAD // AUX: badvaddr
#define HWACHA_CAUSE_FAULT_STORE CAUSE_FAULT_STORE // AUX: badvaddr
#endif

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