diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc
index 90ab5be3..6e030d13 100644
--- a/riscv/cachesim.cc
+++ b/riscv/cachesim.cc
@@ -7,7 +7,7 @@
 #include <iomanip>
 
 cache_sim_t::cache_sim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name)
- : sets(_sets), ways(_ways), linesz(_linesz), name(_name)
+: sets(_sets), ways(_ways), linesz(_linesz), name(_name), log(false)
 {
   init();
 }
@@ -62,7 +62,7 @@ void cache_sim_t::init()
 
 cache_sim_t::cache_sim_t(const cache_sim_t& rhs)
  : sets(rhs.sets), ways(rhs.ways), linesz(rhs.linesz),
-   idx_shift(rhs.idx_shift), name(rhs.name)
+   idx_shift(rhs.idx_shift), name(rhs.name), log(false)
 {
   tags = new uint64_t[sets*ways];
   memcpy(tags, rhs.tags, sets*ways*sizeof(uint64_t));
@@ -135,6 +135,12 @@ void cache_sim_t::access(uint64_t addr, size_t bytes, bool store)
   }
 
   store ? write_misses++ : read_misses++;
+  if (log)
+  {
+    std::cerr << name << " "
+              << (store ? "write" : "read") << " miss 0x"
+              << std::hex << addr << std::endl;
+  }
 
   uint64_t victim = victimize(addr);
 
diff --git a/riscv/cachesim.h b/riscv/cachesim.h
index d597f792..259725ac 100644
--- a/riscv/cachesim.h
+++ b/riscv/cachesim.h
@@ -29,6 +29,7 @@ class cache_sim_t
   void access(uint64_t addr, size_t bytes, bool store);
   void print_stats();
   void set_miss_handler(cache_sim_t* mh) { miss_handler = mh; }
+  void set_log(bool _log) { log = _log; }
 
   static cache_sim_t* construct(const char* config, const char* name);
 
@@ -58,6 +59,7 @@ class cache_sim_t
   uint64_t writebacks;
 
   std::string name;
+  bool log;
 
   void init();
 };
@@ -88,6 +90,10 @@ class cache_memtracer_t : public memtracer_t
   {
     cache->set_miss_handler(mh);
   }
+  void set_log(bool log)
+  {
+    cache->set_log(log);
+  }
 
  protected:
   cache_sim_t* cache;
diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index f922f246..3e5c7e6c 100644
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -32,6 +32,7 @@ static void help()
   fprintf(stderr, "  --ic=<S>:<W>:<B>      Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>        W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>        B both powers of 2).\n");
+  fprintf(stderr, "  --log-cache-miss      Generate a log of cache miss\n");
   fprintf(stderr, "  --extension=<name>    Specify RoCC Extension\n");
   fprintf(stderr, "  --extlib=<name>       Shared library to load\n");
   fprintf(stderr, "  --rbb-port=<port>     Listen on <port> for remote bitbang connection\n");
@@ -89,6 +90,7 @@ int main(int argc, char** argv)
   std::unique_ptr<icache_sim_t> ic;
   std::unique_ptr<dcache_sim_t> dc;
   std::unique_ptr<cache_sim_t> l2;
+  bool log_cache = false;
   std::function<extension_t*()> extension;
   const char* isa = DEFAULT_ISA;
   uint16_t rbb_port = 0;
@@ -126,6 +128,7 @@ int main(int argc, char** argv)
   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
+  parser.option(0, "log-cache-miss", 0, [&](const char* s){log_cache = true;});
   parser.option(0, "isa", 1, [&](const char* s){isa = s;});
   parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
   parser.option(0, "dump-dts", 0, [&](const char *s){dump_dts = true;});
@@ -168,6 +171,8 @@ int main(int argc, char** argv)
 
   if (ic && l2) ic->set_miss_handler(&*l2);
   if (dc && l2) dc->set_miss_handler(&*l2);
+  if (ic) ic->set_log(log_cache);
+  if (dc) dc->set_log(log_cache);
   for (size_t i = 0; i < nprocs; i++)
   {
     if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);