From 0abf98f6f6d5b23b3d23f0c1af0b77b95a199bfe Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 24 May 2023 15:05:38 -0700
Subject: [PATCH] Move setting of V=0 for M-mode trap

So it's right next to set_privilege() which it will be combined with next.
---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6fffc31f..4bcf41f4 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -861,7 +861,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     set_privilege(PRV_S);
   } else {
     // Handle the trap in M-mode
-    set_virt(false);
     const reg_t vector = (state.mtvec->read() & 1) && interrupt ? 4 * bit : 0;
     const reg_t trap_handler_address = (state.mtvec->read() & ~(reg_t)1) + vector;
     // RNMI exception vector is implementation-defined.  Since we don't model
@@ -883,6 +882,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     s = set_field(s, MSTATUS_GVA, t.has_gva());
     state.mstatus->write(s);
     if (state.mstatush) state.mstatush->write(s >> 32);  // log mstatush change
+    set_virt(false);
     set_privilege(PRV_M);
   }
 }