From 08bad17b04320631f2e60af8ea07e04e2af613ac Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Mon, 30 Oct 2023 17:21:40 -0500
Subject: [PATCH] add byte width amo instructions

---
 riscv/insns/amoadd_b.h  | 3 +++
 riscv/insns/amoand_b.h  | 3 +++
 riscv/insns/amocas_b.h  | 4 ++++
 riscv/insns/amomax_b.h  | 3 +++
 riscv/insns/amomaxu_b.h | 3 +++
 riscv/insns/amomin_b.h  | 3 +++
 riscv/insns/amominu_b.h | 3 +++
 riscv/insns/amoor_b.h   | 3 +++
 riscv/insns/amoswap_b.h | 3 +++
 riscv/insns/amoxor_b.h  | 3 +++
 10 files changed, 31 insertions(+)
 create mode 100644 riscv/insns/amoadd_b.h
 create mode 100644 riscv/insns/amoand_b.h
 create mode 100644 riscv/insns/amocas_b.h
 create mode 100644 riscv/insns/amomax_b.h
 create mode 100644 riscv/insns/amomaxu_b.h
 create mode 100644 riscv/insns/amomin_b.h
 create mode 100644 riscv/insns/amominu_b.h
 create mode 100644 riscv/insns/amoor_b.h
 create mode 100644 riscv/insns/amoswap_b.h
 create mode 100644 riscv/insns/amoxor_b.h

diff --git a/riscv/insns/amoadd_b.h b/riscv/insns/amoadd_b.h
new file mode 100644
index 00000000..21381049
--- /dev/null
+++ b/riscv/insns/amoadd_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t lhs) { return lhs + RS2; })));
diff --git a/riscv/insns/amoand_b.h b/riscv/insns/amoand_b.h
new file mode 100644
index 00000000..f461c292
--- /dev/null
+++ b/riscv/insns/amoand_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t lhs) { return lhs & RS2; })));
diff --git a/riscv/insns/amocas_b.h b/riscv/insns/amocas_b.h
new file mode 100644
index 00000000..ca609c72
--- /dev/null
+++ b/riscv/insns/amocas_b.h
@@ -0,0 +1,4 @@
+require_extension('A');
+require_extension(EXT_ZACAS);
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo_compare_and_swap<uint8_t>(RS1, RD, RS2)));
diff --git a/riscv/insns/amomax_b.h b/riscv/insns/amomax_b.h
new file mode 100644
index 00000000..8187a3cc
--- /dev/null
+++ b/riscv/insns/amomax_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](int8_t lhs) { return std::max(lhs, int8_t(RS2)); })));
diff --git a/riscv/insns/amomaxu_b.h b/riscv/insns/amomaxu_b.h
new file mode 100644
index 00000000..534b3ca9
--- /dev/null
+++ b/riscv/insns/amomaxu_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t lhs) { return std::max(lhs, uint8_t(RS2)); })));
diff --git a/riscv/insns/amomin_b.h b/riscv/insns/amomin_b.h
new file mode 100644
index 00000000..c5e8cf97
--- /dev/null
+++ b/riscv/insns/amomin_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](int8_t lhs) { return std::min(lhs, int8_t(RS2)); })));
diff --git a/riscv/insns/amominu_b.h b/riscv/insns/amominu_b.h
new file mode 100644
index 00000000..9bce0e75
--- /dev/null
+++ b/riscv/insns/amominu_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t lhs) { return std::min(lhs, uint8_t(RS2)); })));
diff --git a/riscv/insns/amoor_b.h b/riscv/insns/amoor_b.h
new file mode 100644
index 00000000..f96ff540
--- /dev/null
+++ b/riscv/insns/amoor_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t lhs) { return lhs | RS2; })));
diff --git a/riscv/insns/amoswap_b.h b/riscv/insns/amoswap_b.h
new file mode 100644
index 00000000..5ecbd26e
--- /dev/null
+++ b/riscv/insns/amoswap_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t UNUSED lhs) { return RS2; })));
diff --git a/riscv/insns/amoxor_b.h b/riscv/insns/amoxor_b.h
new file mode 100644
index 00000000..1966bd4a
--- /dev/null
+++ b/riscv/insns/amoxor_b.h
@@ -0,0 +1,3 @@
+require_extension('A');
+require_extension(EXT_ZABHA);
+WRITE_RD((sreg_t)(int8_t)(MMU.amo<uint8_t>(RS1, [&](uint8_t lhs) { return lhs ^ RS2; })));