From 1494468abe7a26efa3ada422fef7f203b41a753a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 14 May 2026 18:41:34 -0700 Subject: [PATCH 1/3] Report triggers on CBOs using effective address, not block address --- riscv/mmu.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/riscv/mmu.h b/riscv/mmu.h index 1ab83647..3c85bc6f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -228,7 +228,7 @@ public: reg_t transformed_addr = access_info.transformed_vaddr; auto base = transformed_addr & ~(blocksz - 1); - check_triggers(triggers::OPERATION_STORE, base, false, blocksz); + check_triggers(triggers::OPERATION_STORE, transformed_addr, false, blocksz); for (size_t offset = 0; offset < blocksz; offset += 1) store(base + offset, 0); } @@ -237,8 +237,7 @@ public: auto access_info = generate_access_info(addr, LOAD, {.clean_inval = true}); reg_t transformed_addr = access_info.transformed_vaddr; - auto base = transformed_addr & ~(blocksz - 1); - check_triggers(triggers::OPERATION_STORE, base, false, blocksz); + check_triggers(triggers::OPERATION_STORE, transformed_addr, false, blocksz); convert_load_traps_to_store_traps({ const reg_t paddr = translate(access_info, 1); if (sim->reservable(paddr)) { From a1d3b43bcae9e754e0fd6544774398809913ab6f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 14 May 2026 18:44:10 -0700 Subject: [PATCH 2/3] Report CBO.ZERO faults on effective address, not base address --- riscv/mmu.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/riscv/mmu.h b/riscv/mmu.h index 3c85bc6f..2e075747 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -227,10 +227,16 @@ public: auto access_info = generate_access_info(addr, STORE, {}); reg_t transformed_addr = access_info.transformed_vaddr; - auto base = transformed_addr & ~(blocksz - 1); check_triggers(triggers::OPERATION_STORE, transformed_addr, false, blocksz); - for (size_t offset = 0; offset < blocksz; offset += 1) - store(base + offset, 0); + + reg_t paddr = translate(access_info, 1); + if (auto host_addr = sim->addr_to_mem(paddr)) { + if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE)) + tracer.trace(paddr - (transformed_addr & (blocksz - 1)), blocksz, STORE); + memset(host_addr - (transformed_addr & (blocksz - 1)), 0, blocksz); + } else { + throw trap_store_access_fault((proc) ? proc->state.v : false, transformed_addr, 0, 0); + } } void clean_inval(reg_t addr, bool clean, bool inval) { From e7a5c9b8f2cc0d75ad74354d0c271209d0f0a048 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 14 May 2026 18:50:50 -0700 Subject: [PATCH 3/3] Invoke memtracer correctly for CBOs --- riscv/mmu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/riscv/mmu.h b/riscv/mmu.h index 2e075747..b0e60ed4 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -229,11 +229,11 @@ public: check_triggers(triggers::OPERATION_STORE, transformed_addr, false, blocksz); - reg_t paddr = translate(access_info, 1); + reg_t paddr = translate(access_info, 1) - (transformed_addr & (blocksz - 1)); if (auto host_addr = sim->addr_to_mem(paddr)) { - if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE)) - tracer.trace(paddr - (transformed_addr & (blocksz - 1)), blocksz, STORE); - memset(host_addr - (transformed_addr & (blocksz - 1)), 0, blocksz); + if (tracer.interested_in_range(paddr, paddr + blocksz, STORE)) + tracer.trace(paddr, blocksz, STORE); + memset(host_addr, 0, blocksz); } else { throw trap_store_access_fault((proc) ? proc->state.v : false, transformed_addr, 0, 0); } @@ -245,9 +245,9 @@ public: check_triggers(triggers::OPERATION_STORE, transformed_addr, false, blocksz); convert_load_traps_to_store_traps({ - const reg_t paddr = translate(access_info, 1); + const reg_t paddr = translate(access_info, 1) - (transformed_addr & (blocksz - 1)); if (sim->reservable(paddr)) { - if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) + if (tracer.interested_in_range(paddr, paddr + blocksz, LOAD)) tracer.clean_invalidate(paddr, blocksz, clean, inval); } else { throw trap_store_access_fault((proc) ? proc->state.v : false, transformed_addr, 0, 0);