rvv: fp16: support element movement instructions

vfmv/vfslide/vfmerge

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/insns/vfmerge_vfm.h

@@ -3,7 +3,20 @@ VI_CHECK_SSS(false);
 VI_VFP_COMMON;
 
 switch(P.VU.vsew) {
-  case 32:
+  case e16:
+    for (reg_t i=P.VU.vstart; i<vl; ++i) {
+      auto &vd = P.VU.elt<float16_t>(rd_num, i, true);
+      auto rs1 = f16(READ_FREG(rs1_num));
+      auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+
+      int midx = (P.VU.vmlen * i) / 64;
+      int mpos = (P.VU.vmlen * i) % 64;
+      bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
+
+      vd = use_first ? rs1 : vs2;
+    }
+    break;
+  case e32:
     for (reg_t i=P.VU.vstart; i<vl; ++i) {
       auto &vd = P.VU.elt<float32_t>(rd_num, i, true);
       auto rs1 = f32(READ_FREG(rs1_num));
@@ -16,7 +29,7 @@ switch(P.VU.vsew) {
       vd = use_first ? rs1 : vs2;
     }
     break;
-  case 64:
+  case e64:
     for (reg_t i=P.VU.vstart; i<vl; ++i) {
       auto &vd = P.VU.elt<float64_t>(rd_num, i, true);
       auto rs1 = f64(READ_FREG(rs1_num));

riscv/insns/vfmv_f_s.h

@@ -1,24 +1,31 @@
 // vfmv_f_s: rd = vs2[0] (rs1=0)
 require_vector;
 require_fp;
-require_extension('F');
-require(P.VU.vsew == e32 || P.VU.vsew == e64);
+require((P.VU.vsew == e16 && p->supports_extension(EXT_ZFH)) ||
+        (P.VU.vsew == e32 && p->supports_extension('F')) ||
+        (P.VU.vsew == e64 && p->supports_extension('D')));
 
 reg_t rs2_num = insn.rs2();
 uint64_t vs2_0 = 0;
 const reg_t sew = P.VU.vsew;
 switch(sew) {
-case e32:
-  vs2_0 = P.VU.elt<uint32_t>(rs2_num, 0);
-  break;
-default:
-  vs2_0 = P.VU.elt<uint64_t>(rs2_num, 0);
-  break;
+  case e16:
+    vs2_0 = P.VU.elt<uint16_t>(rs2_num, 0);
+    break;
+  case e32:
+    vs2_0 = P.VU.elt<uint32_t>(rs2_num, 0);
+    break;
+  case e64:
+    vs2_0 = P.VU.elt<uint64_t>(rs2_num, 0);
+    break;
+  default:
+    require(0);
+    break;
 }
 
 // nan_extened
 if (FLEN > sew) {
-  vs2_0 = vs2_0 | ~((uint64_t(1) << sew) - 1);
+  vs2_0 = vs2_0 | (UINT64_MAX << sew);
 }
 
 if (FLEN == 64) {

riscv/insns/vfmv_s_f.h

@@ -1,21 +1,29 @@
 // vfmv_s_f: vd[0] = rs1 (vs2=0)
 require_vector;
 require_fp;
-require_extension('F');
-require(P.VU.vsew >= e32 && P.VU.vsew <= 64);
+require((P.VU.vsew == e16 && p->supports_extension(EXT_ZFH)) ||
+        (P.VU.vsew == e32 && p->supports_extension('F')) ||
+        (P.VU.vsew == e64 && p->supports_extension('D')));
+
 reg_t vl = P.VU.vl;
 
 if (vl > 0 && P.VU.vstart < vl) {
   reg_t rd_num = insn.rd();
 
   switch(P.VU.vsew) {
-    case 32:
+    case e16:
+      if (FLEN == 64)
+        P.VU.elt<uint16_t>(rd_num, 0, true) = f64(FRS1).v;
+      else
+        P.VU.elt<uint16_t>(rd_num, 0, true) = f32(FRS1).v;
+      break;
+    case e32:
       if (FLEN == 64)
         P.VU.elt<uint32_t>(rd_num, 0, true) = f64(FRS1).v;
       else
         P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v;
       break;
-    case 64:
+    case e64:
       if (FLEN == 64)
         P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v;
       else

riscv/insns/vfmv_v_f.h

@@ -2,6 +2,14 @@
 require((insn.rd() & (P.VU.vlmul - 1)) == 0);
 VI_VFP_COMMON
 switch(P.VU.vsew) {
+  case e16:
+    for (reg_t i=P.VU.vstart; i<vl; ++i) {
+      auto &vd = P.VU.elt<float16_t>(rd_num, i, true);
+      auto rs1 = f16(READ_FREG(rs1_num));
+
+      vd = rs1;
+    }
+    break;
   case e32:
     for (reg_t i=P.VU.vstart; i<vl; ++i) {
       auto &vd = P.VU.elt<float32_t>(rd_num, i, true);

riscv/insns/vfslide1down_vf.h

@@ -4,6 +4,11 @@ VI_CHECK_SLIDE(false);
 VI_VFP_LOOP_BASE
 if (i != vl - 1) {
   switch (P.VU.vsew) {
+    case e16: {
+      VI_XI_SLIDEDOWN_PARAMS(e16, 1);
+      vd = vs2;
+    }
+    break;
     case e32: {
       VI_XI_SLIDEDOWN_PARAMS(e32, 1);
       vd = vs2;
@@ -17,6 +22,9 @@ if (i != vl - 1) {
   }
 } else {
   switch (P.VU.vsew) {
+    case e16:
+      P.VU.elt<float16_t>(rd_num, vl - 1) = f16(FRS1);
+      break;
     case e32:
       P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1);
       break;

riscv/insns/vfslide1up_vf.h

@@ -4,6 +4,11 @@ VI_CHECK_SLIDE(true);
 VI_VFP_LOOP_BASE
 if (i != 0) {
   switch (P.VU.vsew) {
+    case e16: {
+      VI_XI_SLIDEUP_PARAMS(e16, 1);
+      vd = vs2;
+    }
+    break;
     case e32: {
       VI_XI_SLIDEUP_PARAMS(e32, 1);
       vd = vs2;
@@ -17,6 +22,9 @@ if (i != 0) {
   }
 } else {
   switch (P.VU.vsew) {
+    case e16:
+      P.VU.elt<float16_t>(rd_num, 0) = f16(FRS1);
+      break;
     case e32:
       P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1);
       break;