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Merge pull request #1131 from riscv-software-src/zvfh 

Add Spike support for Zvfh and Zvfhmin extensions
pull/1136/head
Scott Johnson 4 years ago
committed by GitHub
parent
6bed230f79 1f1a7da6ba
commit
04a912d8c3
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
20 changed files with 72 additions and 59 deletions
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  1. 2
      riscv/insns/vfmv_f_s.h
  2. 2
      riscv/insns/vfmv_s_f.h
  3. 12
      riscv/insns/vfncvt_f_f_w.h
  4. 14
      riscv/insns/vfncvt_f_x_w.h
  5. 14
      riscv/insns/vfncvt_f_xu_w.h
  6. 12
      riscv/insns/vfncvt_rod_f_f_w.h
  7. 2
      riscv/insns/vfncvt_rtz_x_f_w.h
  8. 2
      riscv/insns/vfncvt_rtz_xu_f_w.h
  9. 2
      riscv/insns/vfncvt_x_f_w.h
  10. 2
      riscv/insns/vfncvt_xu_f_w.h
  11. 12
      riscv/insns/vfwcvt_f_f_v.h
  12. 14
      riscv/insns/vfwcvt_f_x_v.h
  13. 14
      riscv/insns/vfwcvt_f_xu_v.h
  14. 2
      riscv/insns/vfwcvt_rtz_x_f_v.h
  15. 2
      riscv/insns/vfwcvt_rtz_xu_f_v.h
  16. 2
      riscv/insns/vfwcvt_x_f_v.h
  17. 2
      riscv/insns/vfwcvt_xu_f_v.h
  18. 11
      riscv/isa_parser.cc
  19. 2
      riscv/isa_parser.h
  20. 6
      riscv/v_ext_macros.h

2
riscv/insns/vfmv_f_s.h
View File

@ -1,7 +1,7 @@
// vfmv_f_s: rd = vs2[0] (rs1=0)
require_vector(true);
require_fp;
require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZFH)) ||
require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) ||
(P.VU.vsew == e32 && p->extension_enabled('F')) ||
(P.VU.vsew == e64 && p->extension_enabled('D')));
require(STATE.frm->read() < 0x5);

2
riscv/insns/vfmv_s_f.h
View File

@ -1,7 +1,7 @@
// vfmv_s_f: vd[0] = rs1 (vs2=0)
require_vector(true);
require_fp;
require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZFH)) ||
require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) ||
(P.VU.vsew == e32 && p->extension_enabled('F')) ||
(P.VU.vsew == e64 && p->extension_enabled('D')));
require(STATE.frm->read() < 0x5);

12
riscv/insns/vfncvt_f_f_w.h
View File

@ -1,9 +1,9 @@
// vfncvt.f.f.v vd, vs2, vm
VI_VFP_NCVT_FP_TO_FP(
{;}, // BODY16
{ vd = f32_to_f16(vs2); }, // BODY32
{ vd = f64_to_f32(vs2); }, // BODY64
{;}, // CHECK16
{ require_extension(EXT_ZFH); }, // CHECK32
{ require_extension('D'); } // CHECK64
{;}, // BODY16
{ vd = f32_to_f16(vs2); }, // BODY32
{ vd = f64_to_f32(vs2); }, // BODY64
{;}, // CHECK16
{ require_extension(EXT_ZVFHMIN); }, // CHECK32
{ require_extension('D'); } // CHECK64
)

14
riscv/insns/vfncvt_f_x_w.h
View File

@ -1,10 +1,10 @@
// vfncvt.f.x.v vd, vs2, vm
VI_VFP_NCVT_INT_TO_FP(
{;}, // BODY16
{ vd = i32_to_f16(vs2); }, // BODY32
{ vd = i64_to_f32(vs2); }, // BODY64
{;}, // CHECK16
{ require_extension(EXT_ZFH); }, // CHECK32
{ require_extension('F'); }, // CHECK64
int // sign
{;}, // BODY16
{ vd = i32_to_f16(vs2); }, // BODY32
{ vd = i64_to_f32(vs2); }, // BODY64
{;}, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require_extension('F'); }, // CHECK64
int // sign
)

14
riscv/insns/vfncvt_f_xu_w.h
View File

@ -1,10 +1,10 @@
// vfncvt.f.xu.v vd, vs2, vm
VI_VFP_NCVT_INT_TO_FP(
{;}, // BODY16
{ vd = ui32_to_f16(vs2); }, // BODY32
{ vd = ui64_to_f32(vs2); }, // BODY64
{;}, // CHECK16
{ require_extension(EXT_ZFH); }, // CHECK32
{ require_extension('F'); }, // CHECK64
uint // sign
{;}, // BODY16
{ vd = ui32_to_f16(vs2); }, // BODY32
{ vd = ui64_to_f32(vs2); }, // BODY64
{;}, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require_extension('F'); }, // CHECK64
uint // sign
)

12
riscv/insns/vfncvt_rod_f_f_w.h
View File

@ -1,15 +1,15 @@
// vfncvt.rod.f.f.v vd, vs2, vm
VI_VFP_NCVT_FP_TO_FP(
{;}, // BODY16
{ // BODY32
{;}, // BODY16
{ // BODY32
softfloat_roundingMode = softfloat_round_odd;
vd = f32_to_f16(vs2);
},
{ // BODY64
{ // BODY64
softfloat_roundingMode = softfloat_round_odd;
vd = f64_to_f32(vs2);
},
{;}, // CHECK16
{ require_extension(EXT_ZFH); }, // CHECK32
{ require_extension('F'); } // CHECK64
{;}, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require_extension('F'); } // CHECK64
)

2
riscv/insns/vfncvt_rtz_x_f_w.h
View File

@ -3,7 +3,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f16_to_i8(vs2, softfloat_round_minMag, true); }, // BODY16
{ vd = f32_to_i16(vs2, softfloat_round_minMag, true); }, // BODY32
{ vd = f64_to_i32(vs2, softfloat_round_minMag, true); }, // BODY64
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
int // sign

2
riscv/insns/vfncvt_rtz_xu_f_w.h
View File

@ -3,7 +3,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f16_to_ui8(vs2, softfloat_round_minMag, true); }, // BODY16
{ vd = f32_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY32
{ vd = f64_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY64
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
uint // sign

2
riscv/insns/vfncvt_x_f_w.h
View File

@ -3,7 +3,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f16_to_i8(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_i16(vs2, softfloat_roundingMode, true); }, // BODY32
{ vd = f64_to_i32(vs2, softfloat_roundingMode, true); }, // BODY64
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
int // sign

2
riscv/insns/vfncvt_xu_f_w.h
View File

@ -3,7 +3,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f16_to_ui8(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY32
{ vd = f64_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY64
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
uint // sign

12
riscv/insns/vfwcvt_f_f_v.h
View File

@ -1,9 +1,9 @@
// vfwcvt.f.f.v vd, vs2, vm
VI_VFP_WCVT_FP_TO_FP(
{;}, // BODY8
{ vd = f16_to_f32(vs2); }, // BODY16
{ vd = f32_to_f64(vs2); }, // BODY32
{;}, // CHECK8
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension('D'); } // CHECK32
{;}, // BODY8
{ vd = f16_to_f32(vs2); }, // BODY16
{ vd = f32_to_f64(vs2); }, // BODY32
{;}, // CHECK8
{ require_extension(EXT_ZVFHMIN); }, // CHECK16
{ require_extension('D'); } // CHECK32
)

14
riscv/insns/vfwcvt_f_x_v.h
View File

@ -1,10 +1,10 @@
// vfwcvt.f.x.v vd, vs2, vm
VI_VFP_WCVT_INT_TO_FP(
{ vd = i32_to_f16(vs2); }, // BODY8
{ vd = i32_to_f32(vs2); }, // BODY16
{ vd = i32_to_f64(vs2); }, // BODY32
{ require(p->extension_enabled(EXT_ZFH)); }, // CHECK8
{ require_extension('F'); }, // CHECK16
{ require_extension('D'); }, // CHECK32
int // sign
{ vd = i32_to_f16(vs2); }, // BODY8
{ vd = i32_to_f32(vs2); }, // BODY16
{ vd = i32_to_f64(vs2); }, // BODY32
{ require(p->extension_enabled(EXT_ZVFH)); }, // CHECK8
{ require_extension('F'); }, // CHECK16
{ require_extension('D'); }, // CHECK32
int // sign
)

14
riscv/insns/vfwcvt_f_xu_v.h
View File

@ -1,10 +1,10 @@
// vfwcvt.f.xu.v vd, vs2, vm
VI_VFP_WCVT_INT_TO_FP(
{ vd = ui32_to_f16(vs2); }, // BODY8
{ vd = ui32_to_f32(vs2); }, // BODY16
{ vd = ui32_to_f64(vs2); }, // BODY32
{ require(p->extension_enabled(EXT_ZFH)); }, // CHECK8
{ require_extension('F'); }, // CHECK16
{ require_extension('D'); }, // CHECK32
uint // sign
{ vd = ui32_to_f16(vs2); }, // BODY8
{ vd = ui32_to_f32(vs2); }, // BODY16
{ vd = ui32_to_f64(vs2); }, // BODY32
{ require(p->extension_enabled(EXT_ZVFH)); }, // CHECK8
{ require_extension('F'); }, // CHECK16
{ require_extension('D'); }, // CHECK32
uint // sign
)

2
riscv/insns/vfwcvt_rtz_x_f_v.h
View File

@ -4,7 +4,7 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_i32(vs2, softfloat_round_minMag, true); }, // BODY16
{ vd = f32_to_i64(vs2, softfloat_round_minMag, true); }, // BODY32
{;}, // CHECK8
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
int // sign
)

2
riscv/insns/vfwcvt_rtz_xu_f_v.h
View File

@ -4,7 +4,7 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY16
{ vd = f32_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY32
{;}, // CHECK8
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
uint // sign
)

2
riscv/insns/vfwcvt_x_f_v.h
View File

@ -4,7 +4,7 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_i32(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_i64(vs2, softfloat_roundingMode, true); }, // BODY32
{;}, // CHECK8
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
int // sign
)

2
riscv/insns/vfwcvt_xu_f_v.h
View File

@ -4,7 +4,7 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY32
{;}, // CHECK8
{ require_extension(EXT_ZFH); }, // CHECK16
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
uint // sign
)

11
riscv/isa_parser.cc
View File

@ -106,6 +106,17 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
extension_table[EXT_ZFHMIN] = true;
if (ext_str == "zfh")
extension_table[EXT_ZFH] = true;
} else if (ext_str == "zvfh" || ext_str == "zvfhmin") {
if (!((max_isa >> ('v' - 'a')) & 1))
bad_isa_string(str, ("'" + ext_str + "' extension requires 'V'").c_str());
extension_table[EXT_ZVFHMIN] = true;
if (ext_str == "zvfh") {
extension_table[EXT_ZVFH] = true;
// Zvfh implies Zfhmin
extension_table[EXT_ZFHMIN] = true;
}
} else if (ext_str == "zicsr") {
// Spike necessarily has Zicsr, because
// Zicsr is implied by the privileged architecture

2
riscv/isa_parser.h
View File

@ -31,6 +31,8 @@ typedef enum {
EXT_ZBPBO,
EXT_ZPN,
EXT_ZPSFOPERAND,
EXT_ZVFH,
EXT_ZVFHMIN,
EXT_SMEPMP,
EXT_SMSTATEEN,
EXT_SSCOFPMF,

6
riscv/v_ext_macros.h
View File

@ -1474,7 +1474,7 @@ reg_t index[P.VU.vlmax]; \
//
#define VI_VFP_COMMON \
require_fp; \
require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZFH)) || \
require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) || \
(P.VU.vsew == e32 && p->extension_enabled('F')) || \
(P.VU.vsew == e64 && p->extension_enabled('D'))); \
require_vector(true); \
@ -1920,7 +1920,7 @@ reg_t index[P.VU.vlmax]; \
switch (P.VU.vsew) { \
case e16: \
{ VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 16, sign), \
{ p->extension_enabled(EXT_ZFH); }, \
{ p->extension_enabled(EXT_ZVFH); }, \
BODY16); } \
break; \
case e32: \
@ -1944,7 +1944,7 @@ reg_t index[P.VU.vlmax]; \
switch (P.VU.vsew) { \
case e16: \
{ VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 16, sign), \
{ p->extension_enabled(EXT_ZFH); }, \
{ p->extension_enabled(EXT_ZVFH); }, \
BODY16); } \
break; \
case e32: \

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