From 03b47351e69ae954e5b078e18cc10bf21df4712c Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 9 Jun 2023 09:28:15 +0800 Subject: [PATCH] Fix PMP checking region of cache-block management instructions The spec says "The PMP access control bits shall be the same for all physical addresses in the cache block [... else] the behavior of a CBO instruction is UNSPECIFIED." Thus, we only need to check the byte rs1 points to (instead of the entire cache block). --- riscv/mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/mmu.h b/riscv/mmu.h index 5a4835c3..efc6e9de 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -214,7 +214,7 @@ public: void clean_inval(reg_t addr, bool clean, bool inval) { convert_load_traps_to_store_traps({ - const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), blocksz) & ~(blocksz - 1); + const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), 1); if (sim->reservable(paddr)) { if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.clean_invalidate(paddr, blocksz, clean, inval);