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riscv-isa-sim
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Separate RV32 and RV64 C instructions into separate files

pull/1687/head
Andrew Waterman 2 years ago
parent
48f815488e
commit
0325be5559
10 changed files with 31 additions and 33 deletions
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  1. 11
      riscv/insns/c_flw.h
  2. 12
      riscv/insns/c_flwsp.h
  3. 11
      riscv/insns/c_fsw.h
  4. 11
      riscv/insns/c_fswsp.h
  5. 2
      riscv/insns/c_ld.h
  6. 3
      riscv/insns/c_ldsp.h
  7. 2
      riscv/insns/c_sd.h
  8. 2
      riscv/insns/c_sdsp.h
  9. 6
      riscv/overlap_list.h
  10. 4
      riscv/riscv.mk.in

11
riscv/insns/c_flw.h
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@ -1,8 +1,3 @@
if (xlen == 32) { require_extension(EXT_ZCF);
require_extension(EXT_ZCF); require_fp;
require_fp; WRITE_RVC_FRS2S(f32(MMU.load<uint32_t>(RVC_RS1S + insn.rvc_lw_imm())));
WRITE_RVC_FRS2S(f32(MMU.load<uint32_t>(RVC_RS1S + insn.rvc_lw_imm())));
} else { // c.ld
require_extension(EXT_ZCA);
WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));
}

12
riscv/insns/c_flwsp.h
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@ -1,9 +1,3 @@
if (xlen == 32) { require_extension(EXT_ZCF);
require_extension(EXT_ZCF); require_fp;
require_fp; WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm())));
WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm())));
} else { // c.ldsp
require_extension(EXT_ZCA);
require(insn.rvc_rd() != 0);
WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
}

11
riscv/insns/c_fsw.h
View File

@ -1,8 +1,3 @@
if (xlen == 32) { require_extension(EXT_ZCF);
require_extension(EXT_ZCF); require_fp;
require_fp; MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]);
MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]);
} else { // c.sd
require_extension(EXT_ZCA);
MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
}

11
riscv/insns/c_fswsp.h
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@ -1,8 +1,3 @@
if (xlen == 32) { require_extension(EXT_ZCF);
require_extension(EXT_ZCF); require_fp;
require_fp; MMU.store<uint32_t>(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]);
MMU.store<uint32_t>(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]);
} else { // c.sdsp
require_extension(EXT_ZCA);
MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
}

2
riscv/insns/c_ld.h
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@ -0,0 +1,2 @@
require_extension(EXT_ZCA);
WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));

3
riscv/insns/c_ldsp.h
View File

@ -0,0 +1,3 @@
require_extension(EXT_ZCA);
require(insn.rvc_rd() != 0);
WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));

2
riscv/insns/c_sd.h
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@ -0,0 +1,2 @@
require_extension(EXT_ZCA);
MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);

2
riscv/insns/c_sdsp.h
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@ -0,0 +1,2 @@
require_extension(EXT_ZCA);
MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);

6
riscv/overlap_list.h
View File

@ -1,3 +1,9 @@
// these overlap c.ld[sp]/c.sd[sp]
DECLARE_OVERLAP_INSN(c_flw, EXT_ZCF)
DECLARE_OVERLAP_INSN(c_flwsp, EXT_ZCF)
DECLARE_OVERLAP_INSN(c_fsw, EXT_ZCF)
DECLARE_OVERLAP_INSN(c_fswsp, EXT_ZCF)
// these overlap c.fsdsp // these overlap c.fsdsp
DECLARE_OVERLAP_INSN(cm_push, EXT_ZCMP) DECLARE_OVERLAP_INSN(cm_push, EXT_ZCMP)
DECLARE_OVERLAP_INSN(cm_pop, EXT_ZCMP) DECLARE_OVERLAP_INSN(cm_pop, EXT_ZCMP)

4
riscv/riscv.mk.in
View File

@ -182,6 +182,8 @@ riscv_insn_ext_c = \
c_jr \ c_jr \
c_li \ c_li \
c_lui \ c_lui \
c_ld \
c_ldsp \
c_lw \ c_lw \
c_lwsp \ c_lwsp \
c_mv \ c_mv \
@ -191,6 +193,8 @@ riscv_insn_ext_c = \
c_srli \ c_srli \
c_sub \ c_sub \
c_subw \ c_subw \
c_sd \
c_sdsp \
c_sw \ c_sw \
c_swsp \ c_swsp \
c_xor \ c_xor \

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