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rvp: disasm: add simd and register-pair instruction support

pull/2246/head
Jason 4 months ago
committed by Chih-Min Chao
parent
commit
028a698550
  1. 38
      disasm/disasm.cc
  2. 16
      riscv/decode.h
  3. 19
      riscv/decode_macros.h

38
disasm/disasm.cc

@ -538,33 +538,51 @@ struct : public arg_t {
struct : public arg_t { struct : public arg_t {
std::string to_string(insn_t insn) const { std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm2()); return std::to_string((int)insn.p_imm8());
} }
} p_imm2; } p_imm8;
struct : public arg_t { struct : public arg_t {
std::string to_string(insn_t insn) const { std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm3()); return std::to_string((int)insn.p_imm10csl());
} }
} p_imm3; } p_imm10csl;
struct : public arg_t { struct : public arg_t {
std::string to_string(insn_t insn) const { std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm4()); return std::to_string((int)insn.p_imm10csr());
} }
} p_imm4; } p_imm10csr;
struct : public arg_t { struct : public arg_t {
std::string to_string(insn_t insn) const { std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm5()); return std::to_string((int)insn.p_imm10csrw());
} }
} p_imm5; } p_imm10csrw;
struct : public arg_t { struct : public arg_t {
std::string to_string(insn_t insn) const { std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm6()); return std::to_string((int)insn.shamtd());
} }
} p_imm6; } shamtd;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.shamtw());
}
} shamtw;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.shamth());
}
} shamth;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.shamtb());
}
} shamtb;
struct : public arg_t { struct : public arg_t {
std::string to_string(insn_t insn) const { std::string to_string(insn_t insn) const {

16
riscv/decode.h

@ -98,6 +98,9 @@ public:
uint64_t iorw() { return x(20, 8); } uint64_t iorw() { return x(20, 8); }
uint64_t bs() { return x(30, 2); } // Crypto ISE - SM4/AES32 byte select. uint64_t bs() { return x(30, 2); } // Crypto ISE - SM4/AES32 byte select.
uint64_t rcon() { return x(20, 4); } // Crypto ISE - AES64 round const. uint64_t rcon() { return x(20, 4); } // Crypto ISE - AES64 round const.
uint64_t rd_p() { return x(8, 4) * 2; }
uint64_t rs1_p() { return x(16, 4) * 2; }
uint64_t rs2_p() { return x(21, 4) * 2; }
[[maybe_unused]] int64_t rvc_opcode() { return x(0, 2); } [[maybe_unused]] int64_t rvc_opcode() { return x(0, 2); }
int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
@ -148,11 +151,14 @@ public:
uint64_t v_mew() { return x(28, 1); } uint64_t v_mew() { return x(28, 1); }
uint64_t v_zimm6() { return x(15, 5) + (x(26, 1) << 5); } uint64_t v_zimm6() { return x(15, 5) + (x(26, 1) << 5); }
uint64_t p_imm2() { return x(20, 2); } uint64_t p_imm8() { return x(16, 8); }
uint64_t p_imm3() { return x(20, 3); } uint64_t p_imm10csl() { return x(16, 9) + (x(15, 1) << 9); }
uint64_t p_imm4() { return x(20, 4); } uint64_t p_imm10csr() { return (x(24, 1) << 6) + (x(15, 9) << 7); }
uint64_t p_imm5() { return x(20, 5); } uint64_t p_imm10csrw() { return (x(24, 1) << 22) + (x(15, 9) << 23); }
uint64_t p_imm6() { return x(20, 6); } uint64_t shamtd() { return x(20, 6); }
uint64_t shamtw() { return x(20, 5); }
uint64_t shamth() { return x(20, 4); }
uint64_t shamtb() { return x(20, 3); }
uint64_t b_imm5() { return (x(20, 5) == 0) ? -1ul : x(20, 5); } uint64_t b_imm5() { return (x(20, 5) == 0) ? -1ul : x(20, 5); }

19
riscv/decode_macros.h

@ -52,6 +52,23 @@
WRITE_REG((reg) + 1, (sreg_t(val)) >> 32); \ WRITE_REG((reg) + 1, (sreg_t(val)) >> 32); \
} }
// RVP macros
#define WRITE_P_REG_PAIR(reg, value) \
if(reg != 0) { \
uint64_t val = (value); \
WRITE_REG(reg, sext32(val)); \
WRITE_REG((reg) + 1, (sreg_t(val)) >> 32); \
}
#define P_READ_REG_PAIR(reg) ({ \
(reg) == 0 ? reg_t(0) : \
(READ_REG((reg) + 1) << 32) + zext32(READ_REG(reg)); })
#define P_RS1_PAIR P_READ_REG_PAIR(insn.rs1_p())
#define P_RS2_PAIR P_READ_REG_PAIR(insn.rs2_p())
#define P_RD_PAIR P_READ_REG_PAIR(insn.rd_p())
#define WRITE_P_RD_PAIR(value) WRITE_P_REG_PAIR(insn.rd_p(), value)
// RVC macros // RVC macros
#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
@ -219,6 +236,8 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
#define zext(x, pos) (((reg_t)(x) << (64 - (pos))) >> (64 - (pos))) #define zext(x, pos) (((reg_t)(x) << (64 - (pos))) >> (64 - (pos)))
#define sext_xlen(x) sext(x, xlen) #define sext_xlen(x) sext(x, xlen)
#define zext_xlen(x) zext(x, xlen) #define zext_xlen(x) zext(x, xlen)
#define sext_xlen_pair(x) sext(x, xlen * 2)
#define zext_xlen_pair(x) zext(x, xlen * 2)
#define set_pc(x) \ #define set_pc(x) \
do { if (unlikely((x) & ~p->pc_alignment_mask())) \ do { if (unlikely((x) & ~p->pc_alignment_mask())) \

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