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Merge pull request #2146 from riscv-software-src/2144-redux
fix VI_EXT_CHECK vl=0 behavior
pull/1936/head
Andrew Waterman
5 months ago
committed by
GitHub
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GPG Key ID: B5690EEEBB952194
1 changed files with
2 additions and
1 deletions
-
riscv/v_ext_macros.h
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@ -1405,7 +1405,6 @@ VI_VX_ULOOP({ \ |
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#define VI_EXT_CHECK(div) \ |
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require(insn.rd() != insn.rs2()); \ |
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require_vm; \ |
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VI_LOOP_BASE \ |
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reg_t from = P.VU.vsew / div; \ |
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require(from >= e8 && from <= e64); \ |
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require(((float)P.VU.vflmul / div) >= 0.125 && ((float)P.VU.vflmul / div) <= 8 ); \ |
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@ -1420,6 +1419,7 @@ VI_VX_ULOOP({ \ |
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// vector: sign/unsiged extension
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#define VI_VV_EXT(div, type) \ |
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VI_EXT_CHECK(div); \ |
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VI_LOOP_BASE \ |
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reg_t pat = (((P.VU.vsew >> 3) << 4) | from >> 3); \ |
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switch (pat) { \ |
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case 0x21: \ |
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@ -1467,6 +1467,7 @@ VI_VX_ULOOP({ \ |
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#define VI_VF_EXT(div, BODY) \ |
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require(div == 2 && P.VU.vsew == 8); \ |
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VI_EXT_CHECK(div); \ |
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VI_LOOP_BASE \ |
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BODY; \ |
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VI_LOOP_END |
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