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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha/insns_ut_half/ut_fnmadd_h.h

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Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
softfloat_roundingMode = RM;
WRITE_HFRD(f32_mulAdd(HFRS1 ^ (uint32_t)INT32_MIN, HFRS2, HFRS3 ^ (uint32_t)INT32_MIN));
set_fp_exceptions;