riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Spike, a RISC-V ISA Simulator
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
307 Commits
53 Branches
3 Tags
19 MiB
Tree: c258e24c0a
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'c258e24c0a'
${ noResults }
riscv-isa-sim/hwacha/insns_ut_half/ut_fmax_h.h

5 lines
135 B
Raw Normal View History

Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
WRITE_HFRD(isNaNF32UI(HFRS2) || f32_le_quiet(HFRS2,HFRS1) /* && FRS1 not NaN */
? HFRS1 : HFRS2);
set_fp_exceptions;