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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha/insns_ut_half/ut_fcvt_wu_h.h

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Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
softfloat_roundingMode = RM;
WRITE_RD(sext32(f32_to_ui32(HFRS1, RM, true)));
set_fp_exceptions;