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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha/insns_ut_half/ut_fsgnj_h.h

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Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
WRITE_FRD((FRS1 &~ (uint16_t)INT16_MIN) | (FRS2 & (uint16_t)INT16_MIN));