riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Spike, a RISC-V ISA Simulator
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
306 Commits
53 Branches
3 Tags
19 MiB
Tree: 826fc1719a
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '826fc1719a'
${ noResults }
riscv-isa-sim/hwacha/insns_ut_half/ut_fle_h.h

4 lines
63 B
Raw Normal View History

Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
WRITE_RD(f32_le(HFRS1, HFRS2));
set_fp_exceptions;