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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/riscv/insns/psshlr_dhs.h

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rvp: new instructions from 0.20 The complete set of instructions added for RV32 are: PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS And for RV64: PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W reference: https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf https://www.jhauser.us/RISCV/ext-P/RVP-baseInstrs-Sail-020.txt Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2 months ago
require_rv32;
sreg_t sshamt = P_FIELD(RS2, 0, 8);
P_RD_RS1_DW_LOOP(16, 16, {
if (sshamt < 0) {
uint32_t shx;
if (sshamt < -16)
shx = 0;
else if (sshamt == -16)
shx = ((uint16_t)p_rs1 >> 15) & 1;
else
shx = ((uint32_t)(uint16_t)p_rs1 << 1) >> (-sshamt);
p_rd = (uint16_t)((shx + 1) >> 1);
} else {
uint32_t shx = (sshamt >= 16) ? ((uint32_t)(uint16_t)p_rs1 << 16) : ((uint32_t)(uint16_t)p_rs1 << sshamt);
if (shx > 0xFFFF) {
P.VU.vxsat->write(1);
p_rd = 0xFFFF;
} else {
p_rd = (uint16_t)shx;
}
}
})