Spike, a RISC-V ISA Simulator
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/* config.h.in. Generated from configure.ac by autoheader. */
/* Define to the address where bug reports for this package should be sent. */
#undef PACKAGE_BUGREPORT
/* Define to the full name of this package. */
#undef PACKAGE_NAME
/* Define to the full name and version of this package. */
#undef PACKAGE_STRING
/* Define to the one symbol short name of this package. */
#undef PACKAGE_TARNAME
/* Define to the home page for this package. */
#undef PACKAGE_URL
/* Define to the version of this package. */
#undef PACKAGE_VERSION
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef RISCV_ENABLED
/* Define if 64-bit mode is supported */
#undef RISCV_ENABLE_64BIT
/* Define if floating-point instructions are supported */
#undef RISCV_ENABLE_FPU
/* Define if instruction compression is supported */
#undef RISCV_ENABLE_RVC
/* Define if vector processor is supported */
#undef RISCV_ENABLE_VEC
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef SOFTFLOAT_ENABLED
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef SOFTFLOAT_RISCV_ENABLED
/* Define to 1 if you have the ANSI C header files. */
#undef STDC_HEADERS