Spike, a RISC-V ISA Simulator
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/* config.h.in. Generated from configure.ac by autoheader. */
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/* Define to 1 if you have the `fesvr' library (-lfesvr). */
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#undef HAVE_LIBFESVR
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/* Define to 1 if you have the `pthread' library (-lpthread). */
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#undef HAVE_LIBPTHREAD
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/* Define to the address where bug reports for this package should be sent. */
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#undef PACKAGE_BUGREPORT
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/* Define to the full name of this package. */
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#undef PACKAGE_NAME
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/* Define to the full name and version of this package. */
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#undef PACKAGE_STRING
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/* Define to the one symbol short name of this package. */
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#undef PACKAGE_TARNAME
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/* Define to the home page for this package. */
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#undef PACKAGE_URL
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/* Define to the version of this package. */
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#undef PACKAGE_VERSION
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/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
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#undef RISCV_ENABLED
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/* Define if 64-bit mode is supported */
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#undef RISCV_ENABLE_64BIT
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/* Enable commit log generation */
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#undef RISCV_ENABLE_COMMITLOG
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/* Define if floating-point instructions are supported */
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#undef RISCV_ENABLE_FPU
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/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
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#undef SOFTFLOAT_ENABLED
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/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
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#undef SOFTFLOAT_RISCV_ENABLED
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/* Define to 1 if you have the ANSI C header files. */
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#undef STDC_HEADERS
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