riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Spike, a RISC-V ISA Simulator
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
343 Commits
53 Branches
3 Tags
19 MiB
Tree: 0a048a93eb
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '0a048a93eb'
${ noResults }
riscv-isa-sim/hwacha/insns_ut/ut_fcvt_w_h.h

5 lines
107 B
Raw Normal View History

Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
softfloat_roundingMode = RM;
WRITE_RD(sext32(f32_to_i32(HFRS1, RM, true)));
set_fp_exceptions;