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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha/insns_ut/ut_fcvt_h_w.h

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Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
require_fp;
softfloat_roundingMode = RM;
WRITE_HFRD(i32_to_f32((int32_t)RS1));
set_fp_exceptions;