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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/debug_rom/debug_rom.h

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Clean up how Debug ROM is included. I'm not thrilled about including a static copy in so many cc files, and making the compiler throw it out. But without really grokking the Makefile this is the best it's going to be.
10 years ago
static const unsigned char debug_rom_raw[] = {
Add DCSR.MPRVEN support Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status). This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2). This change: * Increases debug specification coverage, allows more detailed testing of external debuggers with Spike. * Decreases the number of required abstract commands to read virtual memory thus improving the user experience. Commit's changes: * Added MPRVEN field to DCSR register * Updated debug_rom.S to turn off MPRVEN on memory access To avoid unwanted address translation while debug_rom.S executed DCSR.MPRVEN bit has to be cleared before and restored after access. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
1 year ago
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Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311) * Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
7 years ago
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Check in compiled debug ROM. Not everybody will have a cross-compiled toolchain set up when they build spike.
10 years ago
};
Add DCSR.MPRVEN support Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status). This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2). This change: * Increases debug specification coverage, allows more detailed testing of external debuggers with Spike. * Decreases the number of required abstract commands to read virtual memory thus improving the user experience. Commit's changes: * Added MPRVEN field to DCSR register * Updated debug_rom.S to turn off MPRVEN on memory access To avoid unwanted address translation while debug_rom.S executed DCSR.MPRVEN bit has to be cleared before and restored after access. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
1 year ago
static const unsigned int debug_rom_raw_len = 260;