This installs the headers to the same place, but for some reason
something on a2 isn't working correctly and is trying to remove the
headers from /usr first.
binutils used to ignore -march when calculating the ELF header. This
means would cause linking problems when trying to link together
libraries generated using the two different ways of specifying the
floating-point ABI.
With this patch, binutils respects -march when it's specified but allows
-msoft-float to override that setting. It's an error to pass
-mhard-float to an ISA without F/D.
It's no longer the case that building the toolchain with
"--disable-float" turns off floating-point by default. This passes the
correct arguments to all the various sub-configures in order to ask for
floating-point support to be either enabled or disabled.
These are cached from riscv-linux and have gotten out of date. The
breaking change was in asm/ptrace.h, but riscv-linux also got bumped so
this is a big commit.
This syncs from e1c1614e7bd2e053e88d0cb875e1a22b27df6e39 in riscv-linux.
I didn't properly check for changes required to support MEMMODEL_SYNC_*, this
looks like the last one I need to make (based on git grep). The rationale is
the same as the previous one.
There was one change required here: support for "MEMMODEL_SYNC_*". This
very long GCC post <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65697>
talks about the formalization of the C++ memory model. It looks like
this is it to allow for some ARM stupidity where they can speculatively
issue some memory operations.
As far as I can tell, the right thing to do here is to just treat the
SYNC versions the same as the non-SYNC versions -- this is the same
thing ia64 and rs600 do. I can't find "MEMMODEL_SYNC" anywhere else
interesting, so there might be some flag to set to avoid doing this, but
I couldn't find it.
LRA is the new register allocator, replacing the complicated reload pass.
It's a much better design, and it seems likely that it will ultimately
replace reload altogether. Rather than contending with the vagaries of
both schemes, I think we should abandon reload altogether.
For RISC-V, LRA seems to have a mixed performance impact, but it will
get better over time.
We have no pattern for moving between a double-precision floating-point
register and an integer register in RV32. This makes the compiler choke.
This workaround raises the cost of those moves significantly. This has
no effect on -O0, which always worked; the other -Ox all seem to work
now. For obvious reasons, this makes me very uncomfortable. But,
as far as I can tell, MIPS is relying on the same behavior.
If this bug rears its head again, no big deal: we can add an "instruction"
for this, which does something like
addi sp, sp, -16
fsd f4, 0(sp)
lw x6, 0(sp)
lw x7, 4(sp)
addi sp, sp, 16
This is heinous, but it's always correct. If the cost model is right,
the compiler will only very rarely invoke it, so the performance cost
of this ingorious hack will be hidden. @palmer-dabbelt
ADDR in this format is only meant to be a symbolic address, not a numeric
address. Things are this way because of linker relaxation. Passing a numeric
address would result in an internal assertion triggering, this patch just makes
gas reject these instructions cleanly.
This compiles glibc on a5 for me. This should fix bug #106.
Andrew Waterman
Palmer Dabbelt
Stefan O'Rear
Colin Schmidt
Andrew Waterman
Scott Beamer
Palmer Dabbelt
Joel Vandergriendt