diff --git a/gcc/gcc/config/riscv/riscv.c b/gcc/gcc/config/riscv/riscv.c
index 660369ff..4cbd6361 100644
--- a/gcc/gcc/config/riscv/riscv.c
+++ b/gcc/gcc/config/riscv/riscv.c
@@ -3534,29 +3534,25 @@ riscv_can_use_return_insn (void)
 static bool
 riscv_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
 {
-  unsigned int size;
-  enum mode_class mclass;
+  unsigned int size = GET_MODE_SIZE (mode);
+  enum mode_class mclass = GET_MODE_CLASS (mode);
 
   /* This is hella bogus but ira_build segfaults on RV32 without it. */
   if (VECTOR_MODE_P (mode))
     return true;
 
-  if (mode == CCmode)
-    return GP_REG_P (regno);
-
-  size = GET_MODE_SIZE (mode);
-  mclass = GET_MODE_CLASS (mode);
-
   if (GP_REG_P (regno))
-    /* Double-word values must be even-register-aligned. */
-    return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
-
-  if (FP_REG_P (regno))
     {
-      /* Allow TFmode for CCmode reloads.  */
-      if (mode == TFmode)
+      if (size <= UNITS_PER_WORD)
 	return true;
 
+      /* Double-word values must be even-register-aligned.  */
+      if (size <= 2 * UNITS_PER_WORD)
+	return regno % 2 == 0;
+    }
+
+  if (FP_REG_P (regno))
+    {
       if (mclass == MODE_FLOAT
 	  || mclass == MODE_COMPLEX_FLOAT
 	  || mclass == MODE_VECTOR_FLOAT)
@@ -4283,6 +4279,12 @@ mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
   emit_insn (gen_clear_cache (addr, end_addr));
 }
 
+static bool
+riscv_lra_p (void)
+{
+  return riscv_lra_flag;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -4410,6 +4412,9 @@ mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
 #undef TARGET_MAX_ANCHOR_OFFSET
 #define TARGET_MAX_ANCHOR_OFFSET (RISCV_IMM_REACH/2-1)
 
+#undef TARGET_LRA_P
+#define TARGET_LRA_P riscv_lra_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/gcc/config/riscv/riscv.md b/gcc/gcc/config/riscv/riscv.md
index 5c050868..4467d3a3 100644
--- a/gcc/gcc/config/riscv/riscv.md
+++ b/gcc/gcc/config/riscv/riscv.md
@@ -1556,12 +1556,12 @@
 })
 
 (define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
-	(match_operand:HI 1 "move_operand"         "r,T,m,rJ"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,*f,*r")
+	(match_operand:HI 1 "move_operand"         "r,T,m,rJ,*r*J,*f"))]
   "(register_operand (operands[0], HImode)
     || reg_or_0_operand (operands[1], HImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,load,store")
+  [(set_attr "move_type" "move,const,load,store,mtc,mfc")
    (set_attr "mode" "HI")])
 
 ;; HImode constant generation; see mips_move_integer for details.
@@ -1597,12 +1597,12 @@
 })
 
 (define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
-	(match_operand:QI 1 "move_operand"         "r,I,m,rJ"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,*f,*r")
+	(match_operand:QI 1 "move_operand"         "r,I,m,rJ,*r*J,*f"))]
   "(register_operand (operands[0], QImode)
     || reg_or_0_operand (operands[1], QImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "move,const,load,store")
+  [(set_attr "move_type" "move,const,load,store,mtc,mfc")
    (set_attr "mode" "QI")])
 
 ;; 32-bit floating point moves
diff --git a/gcc/gcc/config/riscv/riscv.opt b/gcc/gcc/config/riscv/riscv.opt
index b105277c..e43ebab1 100644
--- a/gcc/gcc/config/riscv/riscv.opt
+++ b/gcc/gcc/config/riscv/riscv.opt
@@ -69,3 +69,7 @@ Use hardware atomic memory instructions.
 mmuldiv
 Target Report Mask(MULDIV)
 Use hardware instructions for integer multiplication and division.
+
+mlra
+Target Report Var(riscv_lra_flag) Init(0) Save
+Use LRA instead of reload