From 4e7decfeab58d24185447b3dd7b1699e95afdc2c Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Tue, 16 Jul 2019 23:13:03 -0700 Subject: [PATCH] Bump riscv-gcc backport following patches: - RISC-V: Fix epilogue unwind info with fp and single sp adjust - RISC-V: Generalize -march support, add ELF attribute support. - RISC-V: Add libstdc++ check-abi support. - RISC-V: Fix %lo overflow with BLKmode references. - RISC-V: Add sifive-7 pipeline description. - RISC-V: Fix __riscv_compressed regression. - RISC-V: Promode modes of constant loads for store insns. - RISC-V: Short-forward-branch opt for SiFive 7 series cores. - RISC-V: Move STARTFILE_PREFIX_SPEC into target OS files. - RISC-V: Fix splitter for 32-bit AND on 64-bit target. - https://github.com/riscv/riscv-gcc/issues/161 - Fix typo in riscv_get_interrupt_type and riscv_merge_decl_attributes. - Correctly ignore empty C++ structs when flattening for ABI - Add --disable-tm-clone-registry libgcc configure option. --- riscv-gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-gcc b/riscv-gcc index 8fb74cd0..d1cedda0 160000 --- a/riscv-gcc +++ b/riscv-gcc @@ -1 +1 @@ -Subproject commit 8fb74cd00216817f5d1613e491fdde163aca65bc +Subproject commit d1cedda04973882a412575123cdf04139cbdc8af