From 14087f333d5baedb511935f60844a0b86042ed97 Mon Sep 17 00:00:00 2001
From: Joel Vandergriendt <joel@vectorblox.com>
Date: Mon, 14 Dec 2015 12:35:58 -0800
Subject: [PATCH] replace shift istruction with and instructuction in __mulsi3

An andi instruction is faster on implementations with 1bit per cycle
shifter units.
---
 gcc/libgcc/config/riscv/mul.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/libgcc/config/riscv/mul.S b/gcc/libgcc/config/riscv/mul.S
index 5c935414..f5061b9a 100644
--- a/gcc/libgcc/config/riscv/mul.S
+++ b/gcc/libgcc/config/riscv/mul.S
@@ -11,8 +11,8 @@ __muldi3:
   mv     a2, a0
   li     a0, 0
 .L1:
-  slli   a3, a1, _RISCV_SZPTR-1
-  bgez   a3, .L2
+  andi   a3, a1, 1
+  beqz   a3, .L2
   add    a0, a0, a2
 .L2:
   srli   a1, a1, 1