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@ -231,14 +231,13 @@ struct mips_integer_op { |
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}; |
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/* The largest number of operations needed to load an integer constant.
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The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. |
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When the lowest bit is clear, we can try, but reject a sequence with |
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an extra SLL at the end. */ |
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The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI, |
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but we may attempt and reject even worse sequences. */ |
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#define RISCV_MAX_INTEGER_OPS 32 |
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/* Costs of various operations on the different architectures. */ |
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struct mips_rtx_cost_data |
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struct riscv_tune_info |
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{ |
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unsigned short fp_add; |
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unsigned short fp_mult_sf; |
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@ -249,17 +248,27 @@ struct mips_rtx_cost_data |
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unsigned short int_mult_di; |
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unsigned short int_div_si; |
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unsigned short int_div_di; |
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unsigned short issue_rate; |
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unsigned short branch_cost; |
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unsigned short memory_latency; |
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}; |
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/* Global variables for machine-dependent things. */ |
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/* Information about one CPU we know about. */ |
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struct riscv_cpu_info { |
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/* This CPU's canonical name. */ |
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const char *name; |
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/* The RISC-V ISA and extensions supported by this CPU. */ |
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const char *isa; |
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/* Tuning parameters for this CPU. */ |
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const struct riscv_tune_info *tune_info; |
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}; |
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/* The processor that we should tune the code for. */ |
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enum processor riscv_tune; |
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/* Global variables for machine-dependent things. */ |
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/* Which cost information to use. */ |
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static const struct mips_rtx_cost_data *mips_cost; |
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/* Which tuning parameters to use. */ |
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static const struct riscv_tune_info *tune_info; |
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/* Index [M][R] is true if register R is allowed to hold a value of mode M. */ |
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bool riscv_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; |
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@ -293,43 +302,24 @@ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { |
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FRAME_REGS, FRAME_REGS, |
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}; |
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/* A table describing all the processors GCC knows about. Names are
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matched in the order listed. The first mention of an ISA level is |
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taken as the canonical name for that ISA. |
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To ease comparison, please keep this table in the same order |
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as GAS's riscv_cpu_info_table. Please also make sure that |
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MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march |
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options correctly. */ |
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static const struct riscv_cpu_info riscv_cpu_info_table[] = { |
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/* Entries for generic ISAs. */ |
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{ "rocket", PROCESSOR_ROCKET, 0 }, |
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/* Costs to use when optimizing for size. */ |
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static const struct riscv_tune_info rocket_tune_info = { |
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COSTS_N_INSNS (8), /* fp_add */ |
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COSTS_N_INSNS (8), /* fp_mult_sf */ |
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COSTS_N_INSNS (8), /* fp_mult_df */ |
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COSTS_N_INSNS (20), /* fp_div_sf */ |
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COSTS_N_INSNS (20), /* fp_div_df */ |
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COSTS_N_INSNS (4), /* int_mult_si */ |
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COSTS_N_INSNS (4), /* int_mult_di */ |
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COSTS_N_INSNS (6), /* int_div_si */ |
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COSTS_N_INSNS (6), /* int_div_di */ |
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1, /* issue_rate */ |
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2, /* branch_cost */ |
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7 /* memory_latency */ |
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}; |
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/* Default costs. If these are used for a processor we should look
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up the actual costs. */ |
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#define DEFAULT_COSTS COSTS_N_INSNS (8), /* fp_add */ \ |
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COSTS_N_INSNS (8), /* fp_mult_sf */ \ |
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COSTS_N_INSNS (8), /* fp_mult_df */ \ |
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COSTS_N_INSNS (20), /* fp_div_sf */ \ |
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COSTS_N_INSNS (20), /* fp_div_df */ \ |
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COSTS_N_INSNS (4), /* int_mult_si */ \ |
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COSTS_N_INSNS (4), /* int_mult_di */ \ |
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COSTS_N_INSNS (6), /* int_div_si */ \ |
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COSTS_N_INSNS (6), /* int_div_di */ \ |
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2, /* branch_cost */ \ |
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7 /* memory_latency */ |
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/* Floating-point costs for processors without an FPU. Just assume that
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all floating-point libcalls are very expensive. */ |
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#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ |
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COSTS_N_INSNS (256), /* fp_mult_sf */ \ |
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COSTS_N_INSNS (256), /* fp_mult_df */ \ |
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COSTS_N_INSNS (256), /* fp_div_sf */ \ |
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COSTS_N_INSNS (256) /* fp_div_df */ |
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/* Costs to use when optimizing for size. */ |
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static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { |
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static const struct riscv_tune_info optimize_size_tune_info = { |
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COSTS_N_INSNS (1), /* fp_add */ |
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COSTS_N_INSNS (1), /* fp_mult_sf */ |
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COSTS_N_INSNS (1), /* fp_mult_df */ |
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@ -339,43 +329,30 @@ static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { |
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COSTS_N_INSNS (1), /* int_mult_di */ |
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COSTS_N_INSNS (1), /* int_div_si */ |
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COSTS_N_INSNS (1), /* int_div_di */ |
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1, /* issue_rate */ |
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1, /* branch_cost */ |
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1 /* memory_latency */ |
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}; |
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/* Costs to use when optimizing for speed, indexed by processor. */ |
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static const struct mips_rtx_cost_data |
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mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = { |
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{ /* Rocket */ DEFAULT_COSTS}, |
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/* A table describing all the processors GCC knows about. */ |
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static const struct riscv_cpu_info riscv_cpu_info_table[] = { |
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/* Entries for generic ISAs. */ |
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{ "rocket", "IMAFD", &rocket_tune_info }, |
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}; |
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/* Predicates to test for presence of "near" and "far"/"long_call"
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attributes on the given TYPE. */ |
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/* Return the riscv_cpu_info entry for the given name string. */ |
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static bool |
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mips_near_type_p (const_tree type) |
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{ |
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return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; |
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} |
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static bool |
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mips_far_type_p (const_tree type) |
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static const struct riscv_cpu_info * |
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riscv_parse_cpu (const char *cpu_string) |
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{ |
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return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL |
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|| lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); |
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} |
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unsigned int i; |
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/* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ |
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for (i = 0; i < ARRAY_SIZE (riscv_cpu_info_table); i++) |
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if (strcmp (riscv_cpu_info_table[i].name, cpu_string) == 0) |
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return riscv_cpu_info_table + i; |
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static int |
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mips_comp_type_attributes (const_tree type1, const_tree type2) |
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{ |
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/* Disallow mixed near/far attributes. */ |
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if (mips_far_type_p (type1) && mips_near_type_p (type2)) |
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return 0; |
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if (mips_near_type_p (type1) && mips_far_type_p (type2)) |
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return 0; |
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return 1; |
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error ("unknown cpu `%s'", cpu_string); |
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return riscv_cpu_info_table; |
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} |
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/* Fill CODES with a sequence of rtl operations to load VALUE.
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@ -1435,7 +1412,7 @@ riscv_binary_cost (rtx x, int single_insns, int double_insns, bool speed) |
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static int |
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mips_fp_mult_cost (enum machine_mode mode) |
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{ |
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return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; |
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return mode == DFmode ? tune_info->fp_mult_df : tune_info->fp_mult_sf; |
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} |
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/* Return the cost of floating-point divisions of mode MODE. */ |
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@ -1443,7 +1420,7 @@ mips_fp_mult_cost (enum machine_mode mode) |
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static int |
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mips_fp_div_cost (enum machine_mode mode) |
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{ |
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return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; |
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return mode == DFmode ? tune_info->fp_div_df : tune_info->fp_div_sf; |
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} |
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/* Return the cost of sign-extending OP to mode MODE, not including the
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@ -1541,7 +1518,7 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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cost = riscv_address_insns (addr, mode, true); |
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if (cost > 0) |
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{ |
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*total = COSTS_N_INSNS (cost + mips_cost->memory_latency); |
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*total = COSTS_N_INSNS (cost + tune_info->memory_latency); |
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return true; |
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} |
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/* Otherwise use the default handling. */ |
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@ -1565,7 +1542,7 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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return true; |
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case ABS: |
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*total = float_mode_p ? mips_cost->fp_add : COSTS_N_INSNS (3); |
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*total = float_mode_p ? tune_info->fp_add : COSTS_N_INSNS (3); |
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return false; |
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case LO_SUM: |
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@ -1589,7 +1566,7 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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mode = GET_MODE (XEXP (x, 0)); |
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if (FLOAT_MODE_P (mode)) |
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{ |
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*total = mips_cost->fp_add; |
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*total = tune_info->fp_add; |
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return false; |
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} |
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*total = riscv_binary_cost (x, 1, 3, speed); |
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@ -1631,7 +1608,7 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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if (GET_CODE (XEXP (x, 0)) == MULT) |
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*total = 0; |
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else |
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*total = mips_cost->fp_add; |
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*total = tune_info->fp_add; |
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return false; |
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} |
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@ -1659,7 +1636,7 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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} |
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if (float_mode_p) |
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*total = mips_cost->fp_add; |
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*total = tune_info->fp_add; |
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else |
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*total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); |
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return false; |
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@ -1669,13 +1646,13 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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*total = mips_fp_mult_cost (mode); |
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else if (mode == DImode && !TARGET_64BIT) |
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/* We use a MUL and a MULH[[S]U]. */ |
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*total = mips_cost->int_mult_si * 2; |
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*total = tune_info->int_mult_si * 2; |
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else if (!speed) |
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*total = 1; |
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else if (mode == DImode) |
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*total = mips_cost->int_mult_di; |
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*total = tune_info->int_mult_di; |
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else |
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*total = mips_cost->int_mult_si; |
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*total = tune_info->int_mult_si; |
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return false; |
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case DIV: |
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@ -1693,9 +1670,9 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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if (!speed) |
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*total = 1; |
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else if (mode == DImode) |
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*total = mips_cost->int_div_di; |
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*total = tune_info->int_div_di; |
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else |
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*total = mips_cost->int_div_si; |
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*total = tune_info->int_div_si; |
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return false; |
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case SIGN_EXTEND: |
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@ -1711,7 +1688,7 @@ riscv_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
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case FIX: |
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case FLOAT_EXTEND: |
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case FLOAT_TRUNCATE: |
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*total = mips_cost->fp_add; |
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*total = tune_info->fp_add; |
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return false; |
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default: |
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@ -3728,7 +3705,7 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, |
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static int |
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mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) |
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{ |
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return (mips_cost->memory_latency |
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return (tune_info->memory_latency |
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+ memory_move_secondary_cost (mode, rclass, in)); |
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} |
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@ -3813,16 +3790,9 @@ mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, |
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/* Return the number of instructions that can be issued per cycle. */ |
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static int |
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mips_issue_rate (void) |
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riscv_issue_rate (void) |
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{ |
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switch (riscv_tune) |
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{ |
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case PROCESSOR_ROCKET: |
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return 1; |
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default: |
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return 1; |
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} |
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return tune_info->issue_rate; |
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} |
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/* This structure describes a single built-in function. */ |
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@ -4200,60 +4170,21 @@ mips_init_machine_status (void) |
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return ggc_alloc_cleared_machine_function (); |
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} |
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/* Return the riscv_cpu_info entry for the processor or ISA given
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by CPU_STRING. Return null if the string isn't recognized. |
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A similar function exists in GAS. */ |
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static const struct riscv_cpu_info * |
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mips_parse_cpu (const char *cpu_string) |
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{ |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE (riscv_cpu_info_table); i++) |
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if (strcmp (riscv_cpu_info_table[i].name, cpu_string) == 0) |
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return riscv_cpu_info_table + i; |
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return NULL; |
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} |
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/* Implement TARGET_OPTION_OVERRIDE. */ |
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static void |
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mips_option_override (void) |
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{ |
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int regno, mode; |
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const struct riscv_cpu_info *info; |
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const struct riscv_cpu_info *cpu; |
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#ifdef SUBTARGET_OVERRIDE_OPTIONS |
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SUBTARGET_OVERRIDE_OPTIONS; |
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#endif |
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info = mips_parse_cpu (RISCV_CPU_STRING_DEFAULT); |
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gcc_assert (info); |
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riscv_tune = info->cpu; |
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if (riscv_tune_string != 0) |
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{ |
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const struct riscv_cpu_info *tune = mips_parse_cpu (riscv_tune_string); |
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if (tune) |
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riscv_tune = tune->cpu; |
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} |
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flag_pcc_struct_return = 0; |
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/* Decide which rtx_costs structure to use. */ |
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if (optimize_size) |
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mips_cost = &mips_rtx_cost_optimize_size; |
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else |
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mips_cost = &mips_rtx_cost_data[riscv_tune]; |
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/* If the user hasn't specified a branch cost, use the processor's
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default. */ |
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if (riscv_branch_cost == 0) |
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riscv_branch_cost = mips_cost->branch_cost; |
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if (!TARGET_USE_GP) |
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if (flag_pic) |
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g_switch_value = 0; |
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/* Prefer a call to memcpy over inline code when optimizing for size,
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@ -4261,9 +4192,15 @@ mips_option_override (void) |
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if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) |
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target_flags |= MASK_MEMCPY; |
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/* Use atomic instructions, if user did not specify a preference */ |
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if ((target_flags_explicit & MASK_ATOMIC) == 0) |
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target_flags |= MASK_ATOMIC; |
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/* Handle -mtune. */ |
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cpu = riscv_parse_cpu (riscv_tune_string ? riscv_tune_string : |
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RISCV_TUNE_STRING_DEFAULT); |
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tune_info = optimize_size ? &optimize_size_tune_info : cpu->tune_info; |
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/* If the user hasn't specified a branch cost, use the processor's
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default. */ |
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if (riscv_branch_cost == 0) |
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riscv_branch_cost = tune_info->branch_cost; |
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/* Set up riscv_hard_regno_mode_ok. */ |
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for (mode = 0; mode < MAX_MACHINE_MODE; mode++) |
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@ -4367,7 +4304,7 @@ mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) |
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#undef TARGET_SCHED_ADJUST_COST |
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#define TARGET_SCHED_ADJUST_COST mips_adjust_cost |
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#undef TARGET_SCHED_ISSUE_RATE |
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#define TARGET_SCHED_ISSUE_RATE mips_issue_rate |
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#define TARGET_SCHED_ISSUE_RATE riscv_issue_rate |
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#undef TARGET_FUNCTION_OK_FOR_SIBCALL |
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#define TARGET_FUNCTION_OK_FOR_SIBCALL hook_bool_tree_tree_true |
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@ -4448,9 +4385,6 @@ mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) |
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#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P |
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#define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true |
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#undef TARGET_COMP_TYPE_ATTRIBUTES |
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#define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes |
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#ifdef HAVE_AS_DTPRELWORD |
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#undef TARGET_ASM_OUTPUT_DWARF_DTPREL |
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#define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel |
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Andrew Waterman
11 years ago