riscv/qemu: QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org - qemu

QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org

emulation kvm qemu virtualization

History

Peter Maydell 19b254e86a target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 When we do an AT address translation operation, the page table walk is supposed to be performed in the context of the EL we're doing the walk for, so for instance an AT S1E2R walk is done for EL2. In the pseudocode an EL is passed to AArch64.AT(), which calls SecurityStateAtEL() to find the security state that we should be doing the walk with. In ats_write64() we get this wrong, instead using the current security space always. This is fine for AT operations performed from EL1 and EL2, because there the current security state and the security state for the lower EL are the same. But for AT operations performed from EL3, the current security state is always either Secure or Root, whereas we want to use the security state defined by SCR_EL3.{NS,NSE} for the walk. This affects not just guests using FEAT_RME but also ones where EL3 is Secure state and the EL3 code is trying to do an AT for a NonSecure EL2 or EL1. Use arm_security_space_below_el3() to get the SecuritySpace to pass to do_ats_write() for all AT operations except the AT S1E3* operations. Cc: qemu-stable@nongnu.org Fixes: `e1ee56ec23` ("target/arm: Pass security space rather than flag for AT instructions") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2250 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240405180232.3570066-1-peter.maydell@linaro.org		2 years ago
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alpha	target/alpha: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
arm	target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3	2 years ago
avr	target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
cris	target/cris: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
hexagon	target/hexagon: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
hppa	target/hppa: Clear psw_n for BE on use_nullify_skip path	2 years ago
i386	accel/hvf: Un-inline hvf_arch_supports_guest_debug()	2 years ago
loongarch	target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'	2 years ago
m68k	target/m68k: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
microblaze	target/microblaze: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
mips	target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
nios2	target/nios2: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
openrisc	target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
ppc	target/ppc: Rename init_excp_4xx_softmmu() -> init_excp_4xx()	2 years ago
riscv	target/riscv/kvm: fix timebase-frequency when using KVM acceleration	2 years ago
rx	target/rx: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
s390x	target/s390x: Use mutable temporary value for op_ts	2 years ago
sh4	target/sh4: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
sparc	target/sparc/cpu: Improve the CPU help text	2 years ago
tricore	target/tricore/helper: Use correct string format in cpu_tlb_fill()	2 years ago
xtensa	target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro	2 years ago
Kconfig	hw/loongarch: Add support loongson3 virt machine type.	4 years ago
meson.build	target: Make qemu_target_page_mask() available for *-user	3 years ago
target-common.c	target: Make qemu_target_page_mask() available for *-user	3 years ago