riscv/qemu: QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org - qemu

QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org

Tree: e74818f3cd

History

Paul Brook d4c430a80f Large page TLB flush QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>		16 years ago
..
TODO	target-mips: add copyright notice for mips16 work	17 years ago
cpu.h	Target specific usermode cleanup	16 years ago
exec.h	kill regs_to_env and env_to_regs	16 years ago
helper.c	Large page TLB flush	16 years ago
helper.h	target-mips: use physical address in lladdr	17 years ago
machine.c	target-mips: rename CP0_LLAddr into lladdr	17 years ago
mips-defs.h	target-mips: update address space definitions	16 years ago
op_helper.c	target-mips: don't call cpu_loop_exit() from helper.c	16 years ago
translate.c	target-mips: use newer logical ops	16 years ago
translate_init.c	target-mips: No MIPS16 support for 4Kc, 4KEc cores	17 years ago