riscv/qemu: QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org - qemu

QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org

emulation kvm qemu virtualization

History

Jamin Lin 3dbab141d5 hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" registers to save the high part physical address of Tx/Rx buffer address for master mode. It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers to save the high part physical address of Tx/Rx buffer address for slave mode. Ex: Tx buffer address for master mode [39:0] The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" bits [7:0] which corresponds the bits [39:32] of the 64 bits address of the Tx buffer address. The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the Tx buffer address. Introduce a new has_dma64 class attribute and new registers for the new mode to support DMA 64 bits dram address. Update new mode register number to 28. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>		2 years ago
..
allwinner-i2c.h	hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs	3 years ago
arm_sbcon_i2c.h	hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2C	3 years ago
aspeed_i2c.h	hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses	2 years ago
bcm2835_i2c.h	hw/i2c: Implement Broadcom Serial Controller (BSC)	2 years ago
bitbang_i2c.h	hw/i2c/bitbang_i2c: Define TYPE_GPIO_I2C in public header	3 years ago
i2c.h	hw/i2c: only schedule pending master when bus is idle	3 years ago
i2c_mux_pca954x.h	Clean up ill-advised or unusual header guards	4 years ago
imx_i2c.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	6 years ago
microbit_i2c.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	6 years ago
npcm7xx_smbus.h	hw/i2c: spelling fixes	3 years ago
pm_smbus.h	Include exec/memory.h slightly less	7 years ago
pmbus_device.h	hw/i2c: pmbus: add VCAP register	2 years ago
pnv_i2c_regs.h	ppc/pnv: Test pnv i2c master and connected devices	2 years ago
ppc4xx_i2c.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	6 years ago
smbus_eeprom.h	smbus: Fix spd_data_generate() error API violation	6 years ago
smbus_master.h	i2c: Split smbus into parts	7 years ago
smbus_slave.h	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	6 years ago