riscv/qemu: QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org - qemu

QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org

Tree: 82fcf66e05

History

Stafford Horne d89e71e873 target/openrisc: implement shadow registers Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne <shorne@gmail.com>		9 years ago
..
syscall_nr.h	linux-user: fix TARGET_NR_select	10 years ago
target_cpu.h	target/openrisc: implement shadow registers	9 years ago
target_signal.h	target/openrisc: implement shadow registers	9 years ago
target_structs.h	linux-user: Clean up target_structs.h header guards	10 years ago
target_syscall.h	linux-user: Add MMAP_SHIFT for openrisc	9 years ago
termbits.h	target-or32: Add linux syscall, signal and termbits	14 years ago