riscv/qemu: QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org - qemu

QEMU main repository: Please see https://www.qemu.org/docs/master/devel/submitting-a-patch.html for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website. http://www.qemu.org

emulation kvm qemu virtualization

History

Peter Maydell 28f13bccbe fpu: allow flushing of output denormals to be after rounding Currently we handle flushing of output denormals in uncanon_normal always before we deal with rounding. This works for architectures that detect tininess before rounding, but is usually not the right place when the architecture detects tininess after rounding. For example, for x86 the SDM states that the MXCSR FTZ control bit causes outputs to be flushed to zero "when it detects a floating-point underflow condition". This means that we mustn't flush to zero if the input is such that after rounding it is no longer tiny. At least one of our guest architectures does underflow detection after rounding but flushing of denormals before rounding (MIPS MSA); this means we need to have a config knob for this that is separate from our existing tininess_before_rounding setting. Add an ftz_detection flag. For consistency with tininess_before_rounding, we make it default to "detect ftz after rounding"; this means that we need to explicitly set the flag to "detect ftz before rounding" on every existing architecture that sets flush_to_zero, so that this commit has no behaviour change. (This means more code change here but for the long term a less confusing API.) For several architectures the current behaviour is either definitely or possibly wrong; annotate those with TODO comments. These architectures are definitely wrong (and should detect ftz after rounding): * x86 * Alpha For these architectures the spec is unclear: * MIPS (for non-MSA) * RX * SH4 PA-RISC makes ftz detection IMPDEF, but we aren't setting the "tininess before rounding" setting that we ought to. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>		1 year ago
..
system	i386/cpu: Extract a common fucntion to setup value of MSR_CORE_THREAD_COUNT	1 year ago
user	target/i386: implement SYSCALL/SYSRET in 32-bit emulators	3 years ago
access.c	target/i386: allow access_ptr to force slow path on failed probe	2 years ago
access.h	target/i386: Add tcg/access.[ch]	2 years ago
bpt_helper.c	compiler.h: replace QEMU_NORETURN with G_NORETURN	4 years ago
cc_helper.c	target/i386: use compiler builtin to compute PF	1 year ago
cc_helper_template.h.inc	target/i386: use + to put flags together	1 year ago
decode-new.c.inc	target/i386: Wrap cc_op_live with a validity check	1 year ago
decode-new.h	target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder	1 year ago
emit.c.inc	* target/i386: optimize string instructions	1 year ago
excp_helper.c	include: Rename sysemu/ -> system/	1 year ago
fpu_helper.c	fpu: allow flushing of output denormals to be after rounding	1 year ago
helper-tcg.h	accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core	1 year ago
int_helper.c	target/i386: use compiler builtin to compute PF	1 year ago
mem_helper.c	target/i386: Inline cmpxchg16b	3 years ago
meson.build	include: Rename sysemu/ -> system/	1 year ago
misc_helper.c	target/i386: fix INHIBIT_IRQ/TF/RF handling for PAUSE	2 years ago
mpx_helper.c	i386: move TCG cpu class initialization to tcg/	5 years ago
ops_sse_header.h.inc	target/i386: implement SHA instructions	2 years ago
seg_helper.c	target/i386: Fix legacy page table walk	1 year ago
seg_helper.h	i386: split seg_helper into user-only and sysemu parts	5 years ago
tcg-cpu.c	accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core	1 year ago
tcg-cpu.h	target/i386: Move X86XSaveArea into TCG	5 years ago
tcg-stub.c	i386: move TCG accel files into tcg/	5 years ago
translate.c	target/i386: avoid using s->tmp0 for add to implicit registers	1 year ago